CN-122018622-A - Low-dropout linear voltage regulator circuit with high power supply rejection ratio

Abstract

The invention discloses a low-dropout linear voltage regulator circuit with a high power supply rejection ratio, which comprises an operational amplifier clamping module, a power supply rejection enhancement module and a frequency compensation module, wherein the operational amplifier clamping module comprises a first-stage operational amplifier circuit and a second-stage VBIAS generating circuit which are formed by NMOS transistors and POMS transistors, two stages of circuits are cascaded to form a negative feedback loop for clamping operational amplifier input voltage, the operational amplifier clamping module is connected with a turnover voltage follower for voltage output, the power supply rejection enhancement module is electrically connected with the operational amplifier clamping module and used for carrying out gain on the voltage clamped by the operational amplifier clamping module, the frequency compensation module is electrically connected with the power supply rejection enhancement module and used for carrying out stability compensation on the voltage obtained after the gain of the power supply rejection enhancement module and outputting the voltage after the compensation.

Inventors

• Dang Zhangzhe
• Fu Bonan
• MENG XIAO
• LI DI

Assignees

• 西安电子科技大学

Dates

Publication Date

20260512

Application Date

20260210

Claims (7)

1. 1. The low-dropout linear voltage regulator circuit with high power supply rejection ratio is characterized by comprising an operational amplifier clamping module, a power supply rejection enhancing module and a frequency compensating module; The operational amplifier clamping module comprises a first-stage operational amplifier circuit and a second-stage VBIAS generating circuit which are formed by NMOS transistors and POMS transistors, the two stages of circuits are cascaded to form a negative feedback loop for clamping operational amplifier input voltage, and the operational amplifier clamping module is connected with a turnover voltage follower for voltage output; the power supply suppression enhancing module is electrically connected with the operational amplifier clamping module and is used for gaining the voltage after the operational amplifier clamping module clamps the operational amplifier; The frequency compensation module is electrically connected with the power supply inhibition enhancement module and is used for performing stability compensation on the voltage after the gain of the power supply inhibition enhancement module and outputting the compensated voltage.
2. 2. The low dropout linear regulator circuit according to claim 1, wherein said first stage operational amplifier circuit comprises an NMOS transistor NM1, an NMOS transistor NM2, an NMOS transistor NM3, an NMOS transistor NM4, an NMOS transistor NM5, a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM3, and a PMOS transistor PM4, wherein: The grid end of NM1 is connected with a reference voltage VREF, the source end of NM1 is connected with the source end of NM2 and the drain end of NM3, the drain end of NM1 is connected with the drain end of PM1 and the source end of PM3, the grid end of NM2 is connected with the drain end of PM2 and the source end of PM4, the grid end potential of NM3 is bias voltage VB, the source end of NM3 is connected with power ground GND, the grid end of NM4 is connected with the grid end of NM5 and the grid end of NM3 to output bias voltage VB, the source end of NM4 is connected with power ground GND, the drain end of NM4 is connected with the grid ends of PM1 and PM2 and the drain end of PM3, the source end of NM5 is connected with power ground GND, the drain end of NM5 is connected with the drain end of PM4 and the second-stage VBIAS generating circuit, and the source ends of PM1 and PM2 are connected with the grid ends of power supply VDD, PM3 and PM 4.
3. 3. The low dropout linear regulator circuit according to claim 2, wherein said second stage VBIAS generating circuit comprises a PMOS transistor PM5, a PMOS transistor PM6 and an NMOS transistor NM6; the gate end of PM5 is connected with the drain end of NM5, the drain end of PM5 and the source end of PM6 are connected with the gate end of NM2, the drain end of PM5 is connected with the power supply VDD, and the source end of PM5 is connected with the power supply VDD; The gate end of NM6 is bias voltage VBN and is connected with the turnover voltage follower, the source end of NM6 is connected with power ground GND, and the drain end of NM6 is VBIAS signal and is connected with the gate end, the drain end and the turnover voltage follower of PM 6.
4. 4. A low dropout linear regulator circuit according to claim 3, wherein said op-amp clamp module further comprises a miller compensation capacitor C1, a gate terminal of NM2 is connected to the right side of the capacitor C1, a drain terminal of NM5 is connected to the left side of the capacitor C1, and the signal is ea_out.
5. 5. The low dropout linear regulator circuit according to claim 1, wherein said power supply rejection enhancement module comprises an NMOS transistor NM8, an NMOS transistor NM9, an NMOS transistor NM10, a PMOS transistor PM8, a PMOS transistor PM9, a switch TG1, a switch TG2, a switch TG3, and a module logic control signal; The input signal controlled by the module logic is PSR_ON, the output signal of the signal passing through the first-stage inverter is PSR_EN, and the output signal passing through the second-stage inverter is PSR_ENB; The gate end of NM8 is connected with the left side of the flip voltage follower and the switch TG3, the drain end of NM8 is connected with the gate end of NM9, the drain end of NM9, the gate end of NM10 and the drain end of PM8, the source end of NM8 is connected with the source end of NM9 and the source end of NM10, the source end of PM8 and the source end of PM9 are connected with the power supply VDD, the drain end of NM10 is connected with the drain end of PM9, the flip voltage follower and the right side of TG3, the left sides of TG1 and TG2 are bias voltages VBP, the right side of TG1 is connected with the gate end of PM8, the right side of TG2 is connected with the gate end of PM9, and the control signals of the upper side and the lower side of the switches TG1, TG2 and TG3 are PSR_EN and PSR_ENB.
6. 6. The low dropout linear regulator circuit according to claim 5, wherein said frequency compensation module comprises a switch TG4, a switch TG5, a capacitor Cc, and a resistor Rc; The control signals on the right side and the left side of the TG4 and the TG5 are PSR_EN and PSR_ENB, the upper side of the TG4, the upper polar plate of the capacitor Cc and the flip voltage follower are connected and are the output voltage LDO_OUT, the lower side of the TG4 is connected with the lower-stage plate of the capacitor Cc, the upper side of the TG5 and the upper side of the resistor Rc, and the lower side of the TG5 and the lower side of the resistor Rc are connected with the power ground GND.
7. 7. The low dropout linear regulator circuit according to any one of claims 1 to 6, wherein said flip-flop comprises a PMOS transistor PM7, a PMOS transistor PM10, a PMOS transistor PM11, an NMOS transistor NM7, and an NMOS transistor NM11; Wherein, the gate end of NM11 is connected with the gate end of NM6, the gate end of PM11 is connected with the drain end of NM6, the drain end of NM7 and the drain end of PM7 are connected with the gate end of NM8, the source end of PM10 and the source end of PM7 are connected with the power supply VDD, and the gate end of PM10 is connected with the drain end of NM 10; the gate end of NM7 is bias voltage VSET, the source end of NM7 is connected with drain end of NM11 and drain end of PM11, the source end of NM11 is connected with power ground GND, drain end of PM10, source end of PM11, upper side of switch TG4 and upper polar plate of capacitor Cc are connected into output voltage LDO_OUT.

Description

Low-dropout linear voltage regulator circuit with high power supply rejection ratio Technical Field The invention relates to the technical field of analog integrated circuits, in particular to a low-dropout linear voltage regulator circuit with a high power supply rejection ratio. Background Low dropout linear regulators (LDOs) are powered hearts of analog and mixed signal integrated circuits, whose core task is to provide stable, clean supply voltages for load-sensitive modules such as digital systems, memories, radio frequency modules, and the like. The low cost and easy integration of the off-chip capacitor LDO (Capless LDO) in the chip makes it a key module for the power supply network in the portable device and the SoC of the system on chip, but it faces the serious challenge of poor suppression effect of the mid-high frequency band power supply. The pursuit of higher power supply inhibition effect is the core motive force for pushing the technical evolution, and the prior art mainly goes through several development stages, and has obvious limitations. The conventional high-gain operational amplifier type voltage stabilizer is of the simplest and most classical structure, a negative feedback loop is usually formed by connecting an operational amplifier providing high gain with a power tube in series, the gain of the loop is improved by the operational amplifier of a high gain stage, and the power supply rejection ratio PSRR of a low frequency band is in direct proportion to the loop gain of a circuit, so that the power supply rejection ratio PSRR of a middle frequency band and a low frequency band is improved. The method has the core advantages that excellent power supply rejection ratio PSRR is realized in a low frequency band through high loop gain, and power supply noise can be effectively filtered, however, the cost of the method is huge, and in order to ensure the stability of a loop, the main pole point of the method is required to be arranged at an extremely low frequency, so that the unit gain bandwidth of the system is severely limited, the transient response is slow, and the requirement of rapid load switching cannot be met. More critical, the achievement of stability typically relies on large capacitance external or on-chip capacitors, which is contrary to the original purpose of high-integration, low-cost, off-chip capacitor Capless design. In order to improve the power supply inhibition effect of the voltage stabilizer, the main scheme also comprises a ripple feedforward technology, and the main idea is that the ripple wave change of the input power supply is detected in advance before the main feedback loop reacts to the power supply fluctuation change, a correction signal opposite to the input power supply is generated, and then the power tube is directly driven, so that the influence of the ripple wave on the output is counteracted, and the effect of rapidly processing the ripple wave is achieved. However, this approach has the disadvantage that the feedforward path generates a signal of equal amplitude and opposite phase to the noise, any mismatch will impair the rejection effect, even amplifying the noise and the feedforward path (especially when containing capacitance) will introduce new zeros and poles, changing the frequency response of the loop, and if the compensation is incorrect, reducing the phase margin, causing the system to oscillate. Summarizing, the ripple feed forward technique can significantly improve the power supply rejection ratio PSRR of the mid-to-high band, but improper design may introduce stability problems or poor rejection effects, and the final effect may be inferior to expectations. In order to simplify the design of the circuit, the type of the power tube is also researched and changed, other types of power tubes with better power noise suppression effect, such as NMOS power tubes, are used, even two-stage or multi-stage cascade connection is adopted to realize the step-by-step suppression of the power noise, the power suppression capability of a low-frequency band can be fundamentally improved by using an NMOS power tube or cascade structure method, the total PSRR can be theoretically the sum of PSRRs of all stages, but the cascade structure has some problems, when the NMOS is used as the power tube or the cascade structure is used, the input-output voltage difference can be obviously increased, the efficiency is reduced, and in the application with the requirement of low voltage difference, the circuit has to be additionally provided with a charge pump circuit, so that the complexity of the design of the circuit is greatly increased, the additional noise is introduced, and the chip area and the static power consumption are increased. In summary, the prior art has the following problems that if a traditional high-gain operational amplifier type voltage stabilizer is adopted, a high power supply rejection ratio PSRR can be obtained, but the problems of slo