CN-122018629-A - Chip system and computing method

CN122018629ACN 122018629 ACN122018629 ACN 122018629ACN-122018629-A

Abstract

The invention relates to the technical field of optical calculation, in particular to a chip system and a calculation method, wherein the chip system comprises a glass substrate chip, a matrix input chip and a plurality of matrix multiplication chips are sequentially arranged on the glass substrate chip, a beam splitter is arranged at two ends of the beam splitter and is respectively connected with a light source and the matrix input chip, a first decoupling function area is arranged on the matrix multiplication chip and comprises a plurality of traveling wave guides which are arranged at intervals, the beam splitter is arranged on the traveling wave guides and is connected with a calculation waveguide corresponding to the beam splitter, a modulator is arranged on the calculation waveguide, a second decoupling function area is arranged on the glass substrate chip and corresponds to the matrix multiplication chips, and the second decoupling function area comprises a plurality of column waveguides which are arranged at intervals and is connected with the calculation waveguide through a coupler assembly. The invention provides a large-scale optical computing chip realized based on a decoupling concept, which can improve the computing scale on the basis of realizing process simplification.

Inventors

Cheng Tangsheng
LI WENLING
Pu Huanan
LI ZUOXI

Assignees

光本位智能科技(上海)有限公司

Dates

Publication Date: 20260512
Application Date: 20251203

Claims (10)

1. A chip system, comprising: a PCB (010); A substrate waveguide chip disposed on the PCB; At least one group of matrix operation chips are sequentially arranged on the substrate waveguide chip, and the group of matrix operation chips comprises a matrix input chip (02) with n rows and input columns and a plurality of matrix multiplication chips (03) corresponding to the matrix input chip; The light source device comprises a first beam splitter, a matrix input chip (02) and a matrix multiplication chip (03), wherein two ends of the first beam splitter (01) are respectively connected with a light source (04) and the matrix input chip (02) to divide the light source into at least n optical signals, the n optical signals are respectively input into the matrix input chip (02), the matrix input chip (02) is used for modulating the optical signals to generate corresponding input signals, and the matrix input chip (02) is connected with the matrix multiplication chip (03) to input the input signals into the matrix multiplication chip (03); wherein, be provided with first decoupling function district on matrix multiplication chip (03), first decoupling function district includes: The system comprises a plurality of row waveguides which are arranged at intervals, wherein at least one second beam splitter is arranged on the row waveguides, a row branch waveguide is connected corresponding to the second beam splitter, and a modulator is arranged on the row branch waveguide; a second decoupling function area is arranged on the substrate waveguide chip corresponding to the matrix multiplication chip (03), and the second decoupling function area comprises: A plurality of column waveguides arranged at intervals, and the column waveguides are connected with the row branch waveguides through a coupler assembly; The matrix multiplication chip (03) is used for outputting first incident light formed by the product result of the input signal and the weight signal, the first incident light is transmitted to the column waveguide through the coupler assembly, and the total summation calculation is performed in the column waveguide, and the calculation result is output through the column waveguide.
2. The chip system of claim 1, wherein the matrix input chip is the same as the substrate and waveguide materials of the matrix multiplication chip; And/or the substrate waveguide chip is provided with an optical transmission channel to complete optical signal connection between the matrix input chip and the matrix multiplication chip.
3. The chip system according to claim 1 or 2, wherein the matrix input chip and the matrix multiplication chip are the same chip.
4. The chip system according to claim 1 or 2, wherein the matrix input chip and the matrix multiplication chip are different chips.
5. The chip system of claim 1, wherein the modulator comprises a phase change modulation layer arranged above the row branch line waveguide, a heating layer is arranged above the phase change modulation layer, and a bonding pad is arranged on the heating layer, wherein the bonding pad is used for transmitting an electric signal to the heating layer, and the heat of the heating layer is controlled by the magnitude of the electric signal; and/or at least one first electric chip, and at least one first electric chip is connected with the matrix input chip and/or the matrix multiplication chip.
6. The system on a chip of claim 5, wherein the first decoupling function region further comprises a metal interconnect for connection to a power supply, the metal interconnect being connected to the pad.
7. The chip system of claim 5, wherein the first electrical chip includes or is connected with a power source when the first electrical chip is connected with the matrix multiplication chip.
8. The chip system of claim 1, wherein the substrate waveguide chip is a light transmissive substrate waveguide chip.
9. The chip system of claim 8, wherein the light-transmitting substrate waveguide chip is any one of a glass substrate waveguide chip, a sapphire substrate waveguide chip, an aluminum nitride substrate waveguide chip, and a polymer substrate waveguide chip.
10. A light calculation method implemented by the chip system of any one of claims 1 to 9, comprising the steps of: carrying out primary light splitting on an input light source by utilizing a first beam splitter to obtain n optical signals; The n optical signals are used for being input into n rows and n columns of input chips of the matrix, wherein each 1 row of optical signals is correspondingly divided into 1 column of input signals; Inputting a plurality of columns of input signals into a substrate waveguide chip, and entering a matrix multiplication chip through the substrate waveguide chip; The weight signal is input to a matrix multiplication chip which ultimately outputs a product result obtained by multiplying the input signal and the weight signal.

Description

Chip system and computing method Filing and applying for separate cases The application relates to a patent application of a light calculation chip system and a calculation method, which is filed on the year 2025, month 12 and month 03, and has the application number 2025118048874. Technical Field The invention relates to the technical field of optical computing chips, in particular to a chip system and a computing method. Background The artificial intelligence technology is an important driving force for new technological revolution and industrial revolution, and the basis is intelligent computing force, namely computing system capability for artificial intelligence algorithm model training and model operation. Currently, power scale and energy consumption are key challenges. The power scale depends on the size and communication bandwidth of the interconnection network between the AI accelerators, as well as the performance of the AI accelerators. The main task of the neural network processor in the AI accelerator is matrix operation. Compared with the traditional electric matrix operation, the optical matrix operation has the potential advantages of high-speed parallel processing capability, low delay and low energy consumption. The size of the optical matrix multiplier is limited by the exposure size of the lithography process. Currently, the size of the exposure area of a stepper for preparing optical chips is not more than 2.6cm by 3.3cm. To further expand the computational scale, one approach is based on stitching of the exposed areas of a stepper to expand the chip size, which, however, leads to increased complexity and reduced yields of the lithography process. Another solution is to package a plurality of optoelectronic chips based on 2.5D/3D on the same substrate, and the chips are interconnected by electrical signals, so as to increase the calculation scale. Electrical interconnections between chips increase chip area and power consumption. The optical interconnection can realize high-bandwidth parallel transmission, and the limitation of the size and the energy consumption of the electrical interconnection is broken. For example, patent application CN 117492142a discloses an on-chip optical interconnect structure and a method of making the same, wherein the inter-chip optical interconnect can bridge multiple optoelectronic chips through multiple discrete passive waveguide chips. For another example, patent application CN118732150a discloses a semiconductor structure and a method of manufacturing the same that connects a plurality of optoelectronic chips with a common waveguide substrate. However, after the chip interconnection or the chip scale is increased, the chip design difficulty and the preparation process are both increased significantly, so that the calculation scale is difficult to generate substantial breakthrough. Therefore, a new optical computing chip with lower process complexity and larger computation scale is needed. Disclosure of Invention The invention aims to provide an optical computing chip system and a computing method, which partially solve or alleviate the defects in the prior art, and can improve the computing scale of an optical computing chip to a certain extent and expand the computing performance. In order to solve the technical problems, the invention adopts the following technical scheme: a first aspect of the present invention is to provide an optical computing chip system, including: A PCB board; a glass substrate chip disposed on the PCB; at least one group of matrix operation chips are sequentially arranged on the glass substrate chip, and the group of matrix operation chips comprise matrix input chips with n rows and input columns and a plurality of matrix multiplication chips corresponding to the matrix input chips; the light source is at least split into n light signals, the n light signals are respectively input into the matrix input chip, the matrix input chip is used for modulating the light signals to generate corresponding input signals, and the matrix input chip is connected with the matrix multiplication chip to input the input signals into the matrix multiplication chip; wherein, be provided with first decoupling function district on the matrix multiplication chip, first decoupling function district includes: The system comprises a plurality of row waveguides which are arranged at intervals, wherein at least one second beam splitter is arranged on the row waveguides, a row branch waveguide is connected corresponding to the second beam splitter, and a modulator is arranged on the row branch waveguide; A second decoupling functional area is arranged on the glass substrate chip corresponding to the matrix multiplication chip, and the second decoupling functional area comprises: A plurality of column waveguides arranged at intervals, and the column waveguides are connected with the row branch waveguides through a coupler assembly; The matrix multiplicati