CN-122018630-A - High-resolution sequence pulse synthesizer

CN122018630ACN 122018630 ACN122018630 ACN 122018630ACN-122018630-A

Abstract

The invention relates to the technical field of digital signal generation and high-frequency electronics, and particularly discloses a high-resolution sequence pulse synthesis device, wherein an upper computer configures and transmits sequence pulse parameters, and a data reading control module generates a ground state control data stream according to the parameters; the programmable edge fine tuning module generates multipath control data flow by adopting a multichannel collaborative fine tuning algorithm according to the number of edge offset steps, the data split-phase transmitting module converts the control data flow into multipath phase staggered high-speed serial signals by utilizing a plurality of reference clock channels with sequentially offset phases, and finally synthesizes one path of high-speed serial pulse signals with ultrahigh time resolution through an OR gate. The invention breaks through the resolution limit of a single clock domain, realizes independent and accurate programming of any edge in a pulse sequence, can generate sequence pulses with large data volume, high output frequency and extremely high resolution, and is suitable for high-performance scenes such as communication, semiconductor test and the like.

Inventors

FU ZAIMING
WANG RUIQI
LIU HANGLIN
AI XIN

Assignees

电子科技大学

Dates

Publication Date: 20260512
Application Date: 20260119

Claims (8)

1. The high-resolution sequence pulse synthesis device is characterized by comprising an upper computer, a pulse data memory, a frequency configuration register, a fine adjustment enabling register, an edge offset memory, a data reading control module, a programmable edge fine adjustment module, a data split-phase sending module and an OR gate; The upper computer is used for configuring and transmitting sequence pulse parameters, wherein the sequence pulse parameters comprise sequence pulse data Reference pulse frequency Edge fine adjustment enable signal Edge offset step number set ; The pulse data memory, the frequency configuration register, the fine adjustment enabling register and the edge offset memory are respectively used for receiving and storing the sequence pulse data issued by the upper computer Reference pulse frequency Edge fine adjustment enable signal Edge offset step number set ; A data reading control module for reading the sequence pulse data from the pulse data memory And reads out the reference pulse frequency from the frequency configuration register According to the reference pulse frequency Calculating the number of sample points per user pulse And according to the number of sampling points Converting sequence pulse into ground state control data stream in real time Control data flow of ground state And the number of sampling points Outputting to a programmable edge fine adjustment module; A programmable edge fine tuning module for fine tuning the enable signal according to the edge output from the fine tuning enable register Determining whether to enable the edge fine tuning function, and controlling the data stream for the ground state when the edge fine tuning function is enabled Each detected edge in the sequence is read out from an edge offset memory, and a multi-channel collaborative fine tuning algorithm is applied to generate The path control data flows to the data split-phase sending module; wherein the multichannel collaborative fine tuning algorithm takes pulse width units as processing units, and each pulse width unit corresponds to a ground state control data stream The middle time length is A group of cooperative parameters for cooperatively controlling multiple paths of data channels are obtained by decomposition and calculation according to the number of edge offset steps configured for the starting edge and the ending edge of the current pulse width unit, and the data stream is controlled in the ground state according to the cooperative parameters On the basis of (1) generating A path control data stream including a main channel control data stream for realizing coarse adjustment of integer multiple of reference clock period, and Road for implementing system time resolution Auxiliary channel control data flow with fine-tuning level; The data split-phase transmitting module comprises The channels use reference clocks with the same frequency but with the phase sequentially delayed by a specific proportion, and the received reference clocks are respectively transmitted to the channels The corresponding way in the way control data stream is converted into a group of ways A high-speed serial signal with sequentially shifted path phases; Or gate for connecting the The high-speed serial signals with sequentially offset phases are logically or combined to output a high-resolution sequence pulse signal with the time resolution of the reference clock period 。
2. The high resolution sequential pulse synthesis apparatus according to claim 1, wherein said multi-channel collaborative fine tuning algorithm locally comprises an offset decomposition step and a control data stream generation step: and (3) an offset decomposition step: For the first Pulse width units for shifting steps according to their initial edges And ending edge offset step number Calculating a set for generating the The cooperative parameters of the path control data stream include offset steps for coarse tuning of the main channel Auxiliary channel index for indicating participation in fine tuning And a sample point position index for indicating an insertion position of a fine-narrowing pulse in the auxiliary channel data stream ; A control data stream generating step: According to the cooperative parameters 、、 Generating the said Way control data flow , wherein, The data stream is controlled for the main channel, Control data flow for auxiliary channel and control data flow for main channel For coarse adjustment of edges by integer multiples of the reference clock period, the first Data values within a pulse width cell are based on And Modifying the value of (2) to realize the delay or advance of the edge in a mode of covering the ground state data; Auxiliary channel control data flow Only if the channel index is satisfied Equal to the auxiliary channel index On the condition that the auxiliary channel controls the data stream Index within each pulse width unit is Setting the data value to generate a fine-tuning pulse for achieving the system time resolution, otherwise, the control data stream maintains the default data value at said location Edge trimming at the level.
3. The high resolution sequential pulse synthesizer of claim 2, wherein the co-parameters are 、 And The specific calculation method of (a) is as follows: ; ; ; Wherein, the Representing a rounding operation.
4. A high resolution sequential pulse synthesis apparatus according to claim 3, wherein the main channel controls the data stream For coarse adjustment of edges by integer multiples of the reference clock period, the first Data values within a pulse width cell are based on And The specific method for modifying the value of (2) is as follows: ; for the index of the sampling points within the pulse width unit, ; Representing a main channel control data stream Middle (f) The index of each pulse width unit is Is used for the sampling points of the (a), The data stream is controlled for the ground state.
5. The apparatus of claim 4, wherein the auxiliary channel controls the data stream Only if the channel index is satisfied Equal to the auxiliary channel index On the condition that the auxiliary channel controls the data stream Index within each pulse width unit is The specific method for setting the data value to generate a fine-narrowing pulse is as follows: Controlling data flow for auxiliary channel Wherein fine tuning control data stream index Using the kronecker function And (3) performing positioning assignment: ; Wherein, the Indicating when The value is 1, otherwise, the value is 0.
6. The high resolution sequential pulse synthesizer of claim 1, wherein the set of edge offset steps Number of steps per edge offset in (a) By the user as the first Physical time offset of each edge configuration divided by the system time resolution And rounding to obtain the product.
7. The apparatus according to claim 1, wherein the index in the data split-phase transmission module is Phase offset on the data transmission channels of (a) is , wherein, For the index of the data transmission channel, The corresponding time delay is , For the reference clock cycle to be a reference, Is the reference clock frequency.
8. The high resolution sequential pulse synthesizer of claim 1, wherein said or gate is a high speed logic or gate by integrating said or gate with said high resolution sequential pulse synthesizer The high-speed serial signals with sequentially shifted paths are logically or combined, so that the edge time of the finally output high-resolution sequence pulse signals is jointly determined by the rising edge of the channel which is changed into high level at the earliest and the falling edge of the channel which is changed into low level at the latest, and the delay effect of the multipath signals is superposed on one path.

Description

High-resolution sequence pulse synthesizer Technical Field The invention relates to digital signal generation and high-frequency electronic technology, in particular to a high-resolution sequence pulse synthesis device. Background The pulse signal generator is a core device in the field of electronic testing and measurement, and the sequence pulse generating function is important in the fields of communication, semiconductor, particle physics and the like. A sequence of pulses is a sequence of digital signals consisting of a series of pulses following a specific coding rule. With the rapid development of semiconductor technology and integrated circuit scale, electronic test scenarios place higher demands on the performance of sequential pulses, including larger data volumes, higher output frequencies, and time resolution on the order of nanoseconds or picoseconds. Currently, the technology based on direct digital synthesis DDS is a mainstream scheme for digitally generating sequence pulses, and is mainly divided into two types, namely direct digital waveform synthesis DDWS and direct digital frequency synthesis DDFS. DDWS techniques pre-compute and store all samples of the waveform in memory, read out sequentially at output, while DDFS techniques generate signals through phase accumulators and waveform look-up tables. However, both of these approaches, when dealing with the high performance sequential pulse generation requirements, expose a series of inherent drawbacks: firstly, in terms of storage depth and waveform flexibility, DDWS and DDFS need to store massive sampling point data when generating aperiodic, large data volume or complex coded pulse sequences, which greatly increases the storage burden and implementation difficulty of the system and lacks efficiency and economy. Second, in terms of real-time and output bandwidth, since each sampling point needs to be read from the memory, the highest output frequency of the sequence pulse is directly limited by the reading speed of the memory. However, to achieve extremely high read frequency, it is a significant challenge in terms of technology and cost, and it is a bottleneck to increase output bandwidth. Furthermore, DDWS must change the system clock frequency or update the entire waveform memory to change the output frequency in terms of output control and resolution, both of which result in output interruption, lack of flexibility of dynamic adjustment, and limited fine control over high resolution. While DDFS can achieve continuous variation of output frequency by changing frequency control words, its adjustment target is the frequency of the entire waveform, making it difficult to quickly, independently and accurately modulate the width of a single pulse or the position of a particular edge. Finally, in terms of time resolution, the conventional digital method is limited to a single clock domain, the minimum time step cannot exceed one reference clock period, and picosecond resolution is difficult to achieve by breaking the hardware limit. Although there are techniques for fine tuning using analog delay lines, there are common disadvantages of low accuracy, large temperature drift, difficulty in digital programming and control, etc. Disclosure of Invention The invention aims to solve the technical problem of providing a sequential pulse generation scheme which can simultaneously meet the requirements of large data volume, high output frequency and high time resolution and can program the edges of pulses in real time, independently and accurately. The invention adopts the technical scheme that the high-resolution sequence pulse synthesis device comprises an upper computer, a pulse data memory, a frequency configuration register, a fine adjustment enabling register, an edge offset memory, a data reading control module, a programmable edge fine adjustment module, a data split-phase transmission module and an OR gate: the device comprises an upper computer, a pulse data memory, a frequency configuration register, a fine adjustment enabling register, an edge offset memory, a data reading control module, a programmable edge fine adjustment module, a data split-phase sending module and an OR gate; The upper computer is used for configuring and transmitting sequence pulse parameters, wherein the sequence pulse parameters comprise sequence pulse data Reference pulse frequencyEdge fine adjustment enable signalEdge offset step number set; The pulse data memory, the frequency configuration register, the fine adjustment enabling register and the edge offset memory are respectively used for receiving and storing the sequence pulse data issued by the upper computerReference pulse frequencyEdge fine adjustment enable signalEdge offset step number set; A data reading control module for reading the sequence pulse data from the pulse data memoryAnd reads out the reference pulse frequency from the frequency configuration registerAccording to the reference pulse freque