CN-122018631-A - Dynamic frequency multiplication method and device for time measurement unit

CN122018631ACN 122018631 ACN122018631 ACN 122018631ACN-122018631-A

Abstract

The application relates to a dynamic frequency multiplication method and device for a time measurement unit. The method comprises the steps of determining an input clock domain range and the maximum frequency multiplication frequency of a mixed clock manager, and determining a frequency multiplication coefficient, a frequency division coefficient and segmentation information corresponding to each frequency multiplication coefficient and the frequency division coefficient under the constraint that the frequency multiplication coefficient, the frequency division coefficient and the overall frequency multiplication coefficient of the mixed clock manager are integers based on the input clock domain range and the maximum frequency multiplication frequency of the mixed clock manager, wherein the frequency multiplication coefficient and the frequency division coefficient are used for generating sampling clock waveforms of a time measurement unit. The method can solve the problem that measurement cannot be triggered synchronously by measurement of the TMU of the cross-sub board.

Inventors

WEI XIN
BAI TONG
TANG LONG

Assignees

杭州长川科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260410

Claims (12)

1. A method of dynamic frequency doubling of a time measurement unit, applied to a drive, comprising: Determining an input clock domain range and a maximum multiplication frequency of a mixed clock manager; and determining a frequency multiplication coefficient and a frequency division coefficient and segmentation information corresponding to each frequency multiplication coefficient and the frequency division coefficient under the constraint that the frequency multiplication coefficient, the frequency division coefficient and the overall frequency multiplication coefficient of the hybrid clock manager are integers based on the input clock domain range and the maximum frequency multiplication frequency of the hybrid clock manager, wherein the frequency multiplication coefficient and the frequency division coefficient are used for generating sampling clock waveforms of the time measurement unit.
2. The method of claim 1, wherein determining the multiplication factor and the division factor and the segment information for each of the multiplication factor and the division factor based on the input clock domain range and the maximum multiplication frequency of the hybrid clock manager, and under the constraint that the multiplication factor, the division factor, and the overall multiplication factor of the hybrid clock manager are integers, comprises: Determining an expected time measurement sampling clock frequency range; And under the constraint that the frequency multiplication frequency of the mixed clock manager is smaller than or equal to the maximum frequency multiplication frequency and the frequency multiplication coefficient is maximized, determining the frequency multiplication coefficient and the segmentation information corresponding to each frequency multiplication coefficient and the frequency multiplication coefficient based on the expected time measurement sampling clock frequency range and the input clock domain range.
3. The method of claim 2, wherein the determining the multiplication factor and the division factor and the segment information corresponding to each of the multiplication factor and the division factor based on the expected time measurement sampling clock frequency range and the input clock domain range comprises: Measuring the maximum value of the sampling clock frequency range and the minimum value of the input clock domain range based on the expected time, and determining the value range of the integral frequency multiplication coefficient under the constraint that the integral frequency multiplication coefficient is an integer; For each integral frequency multiplication coefficient in the value range of the integral frequency multiplication coefficient, determining segmentation information based on the expected time measurement sampling clock frequency range; Based on the maximum frequency and the segmentation information, determining a value range of a frequency multiplication coefficient under the constraint that the frequency multiplication frequency of the mixed clock manager is smaller than or equal to the maximum frequency multiplication frequency; And determining the frequency multiplication coefficient and the frequency division coefficient under the constraint that the frequency multiplication coefficient and the frequency division coefficient of the mixed clock manager are integers and the frequency multiplication coefficient is maximized based on the value range of the frequency multiplication coefficient and the integral frequency multiplication coefficient.
4. A method according to claim 3, wherein said measuring the maximum value of the sampling clock frequency range, the minimum value of the input clock domain range, and determining the range of values of the overall multiplication factor under the constraint that the overall multiplication factor be an integer, based on the expected time, comprises: Determining a maximum value of an overall frequency multiplication coefficient based on the maximum value of the sampling clock frequency range and the minimum value of the input clock domain range measured at the expected time; Determining the minimum value of the integral frequency multiplication coefficient based on the quinine-Nernst sampling law, the frequency of a signal to be detected output by a chip to be detected and the minimum value of an input clock domain range; and determining the value range of the integral frequency multiplication coefficient according to the maximum value and the minimum value of the integral frequency multiplication coefficient.
5. A method according to claim 3, wherein said determining segment information for each of said range of values of integral multiplication coefficients based on a range of sample clock frequencies measured at an expected time comprises: For each integral frequency multiplication coefficient in the value range of the integral frequency multiplication coefficient, determining segmentation information based on the quotient of the sampling clock frequency range and the integral frequency multiplication coefficient measured at expected time.
6. The method of claim 3, wherein the determining the multiplication factor and the division factor based on the range of values of the multiplication factor and the overall multiplication factor under the constraint that the multiplication factor and the division factor of the hybrid clock manager are integers and maximize the multiplication factor comprises: Based on determining a maximum frequency multiplication coefficient divided by the overall frequency multiplication coefficient, wherein the maximum frequency multiplication coefficient is an integer, and the maximum frequency multiplication coefficient is less than or equal to a maximum value of a value range of the frequency multiplication coefficient; a frequency division coefficient is determined based on the maximum frequency multiplication coefficient and the overall frequency multiplication coefficient.
7. The method according to claim 1, wherein the method further comprises: and determining a maximum sampling period of the time measurement unit based on the segmentation information, wherein the maximum sampling period is used for indicating an FPGA to set the total delay of a carry chain to be larger than the maximum sampling period.
8. The method according to claim 1, wherein the method further comprises: Acquiring a current input clock domain range; And determining a target frequency multiplication coefficient and a target frequency division coefficient corresponding to the current input clock domain range based on the current input clock domain range and the pre-generated segmentation information.
9. The method according to claim 8, characterized in that the method comprises: receiving configuration parameter values; And determining a corresponding cross-sub-board synchronous triggering frequency multiplication rule based on the configuration parameter value, wherein the step of acquiring the current input clock domain range is continuously executed under the condition that the cross-sub-board synchronous triggering mode is determined based on the configuration parameter value.
10. The dynamic frequency doubling method of the time measurement unit is characterized by being applied to an FPGA and comprising the following steps of: Receiving a frequency multiplication coefficient and a frequency division coefficient determined based on the dynamic frequency multiplication method of the time measurement unit according to any one of claims 1 to 9; And generating a sampling clock waveform corresponding to the time measurement unit based on the frequency multiplication coefficient and the frequency division coefficient.
11. A time measurement cell dynamic frequency doubling device for use in driving, the device comprising: The input acquisition module is used for determining an input clock domain range and the maximum multiplication frequency of the mixed clock manager; The segmentation information determining module is used for determining the frequency multiplication coefficient and the frequency division coefficient and the segmentation information corresponding to each frequency multiplication coefficient and the frequency division coefficient based on the input clock domain range and the maximum frequency multiplication frequency of the mixed clock manager under the constraint that the frequency multiplication coefficient, the frequency division coefficient and the integral frequency multiplication coefficient of the mixed clock manager are integers, and the frequency multiplication coefficient and the frequency division coefficient are used for generating sampling clock waveforms of the time measurement unit.
12. A time measurement unit dynamic frequency doubling device, characterized by being applied to an FPGA, said device comprising: A receiving module for receiving the frequency multiplication coefficient and the frequency division coefficient determined based on the time measurement unit dynamic frequency multiplication device according to claim 11; And the sampling clock waveform generation module is used for generating a sampling clock waveform corresponding to the time measurement unit based on the frequency multiplication coefficient and the frequency division coefficient.

Description

Dynamic frequency multiplication method and device for time measurement unit Technical Field The application relates to the technical field of semiconductors, in particular to a dynamic frequency multiplication method and device for a time measurement unit. Background The clock for the TMU module of the digital board is often coupled to DomainClk (tester master clock) of other services, in the conventional technology, the waveform of the TMU sampling clock is obtained by DomainClk multiplying by MMCM (Mixed-mode clock manager ), if the integral multiplication coefficient of the MMCM is a decimal, it may result in that when Delay measurement is performed between sub-board channels of the digital board, the TMUs on two sub-boards cannot trigger measurement at the same time, and thus the Delay measurement may be worse than expected by one TMU sampling clock waveform period. Disclosure of Invention Based on this, it is necessary to provide a method and a device for dynamic frequency multiplication of a time measurement unit capable of guaranteeing synchronous triggering of measurement across sub-boards in order to solve the above technical problems. In a first aspect, the present application provides a dynamic frequency doubling method of a time measurement unit, applied to driving, including: Determining an input clock domain range and a maximum multiplication frequency of a mixed clock manager; and determining a frequency multiplication coefficient and a frequency division coefficient and segmentation information corresponding to each frequency multiplication coefficient and the frequency division coefficient under the constraint that the frequency multiplication coefficient, the frequency division coefficient and the overall frequency multiplication coefficient of the hybrid clock manager are integers based on the input clock domain range and the maximum frequency multiplication frequency of the hybrid clock manager, wherein the frequency multiplication coefficient and the frequency division coefficient are used for generating sampling clock waveforms of the time measurement unit. In one embodiment, the determining the frequency multiplication coefficient and the frequency division coefficient and the segment information corresponding to each frequency multiplication coefficient and the frequency division coefficient under the constraint that the frequency multiplication coefficient, the frequency division coefficient and the overall frequency multiplication coefficient of the hybrid clock manager are all integers based on the input clock domain range and the maximum frequency multiplication frequency of the hybrid clock manager includes: Determining an expected time measurement sampling clock frequency range; And under the constraint that the frequency multiplication frequency of the mixed clock manager is smaller than or equal to the maximum frequency multiplication frequency and the frequency multiplication coefficient is maximized, determining the frequency multiplication coefficient and the segmentation information corresponding to each frequency multiplication coefficient and the frequency multiplication coefficient based on the expected time measurement sampling clock frequency range and the input clock domain range. In one embodiment, the determining the frequency multiplication coefficient and the frequency division coefficient and the segment information corresponding to each frequency multiplication coefficient and the frequency division coefficient based on the expected time measurement sampling clock frequency range and the input clock domain range includes: Measuring the maximum value of the sampling clock frequency range and the minimum value of the input clock domain range based on the expected time, and determining the value range of the integral frequency multiplication coefficient under the constraint that the integral frequency multiplication coefficient is an integer; For each integral frequency multiplication coefficient in the value range of the integral frequency multiplication coefficient, determining segmentation information based on the expected time measurement sampling clock frequency range; Based on the maximum frequency and the segmentation information, determining a value range of a frequency multiplication coefficient under the constraint that the frequency multiplication frequency of the mixed clock manager is smaller than or equal to the maximum frequency multiplication frequency; And determining the frequency multiplication coefficient and the frequency division coefficient under the constraint that the frequency multiplication coefficient and the frequency division coefficient of the mixed clock manager are integers and the frequency multiplication coefficient is maximized based on the value range of the frequency multiplication coefficient and the integral frequency multiplication coefficient. In one embodiment, the measuring the maximum value of the sampling clock frequ