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CN-122018633-A - Working frequency adjusting method based on cache, processor and electronic equipment

CN122018633ACN 122018633 ACN122018633 ACN 122018633ACN-122018633-A

Abstract

The application provides a working frequency adjusting method based on cache, a processor and electronic equipment, and relates to the field of integrated circuits. The method for adjusting the working frequency based on the cache comprises the steps of receiving an adjusting instruction for adjusting the working frequency of the processor, disabling the phase-locked loop and adjusting the phase-locked loop based on the adjusting instruction, wherein the cache receives a request of the processing core and the connection framework component and limits the request to be sent to the memory controller so as to limit the processing core to call the memory in the process of adjusting the phase-locked loop. The method can reduce the abnormality caused by too low working frequency due to switching of the clock source in the process of adjusting the working frequency of the processor.

Inventors

  • Ai Xueting
  • MA XIAO

Assignees

  • 上海天数智芯半导体股份有限公司

Dates

Publication Date
20260512
Application Date
20250820

Claims (14)

  1. 1. The buffer memory-based working frequency adjusting method is characterized by being used for adjusting the working frequency of a processor; The processor comprises a processing core, a connection framework component, a cache, a memory controller and a memory which are sequentially connected, and also comprises a phase-locked loop, wherein the phase-locked loop is connected with the processing core; the phase-locked loop is used for providing a clock signal for the processing core so that the processing core works based on the clock signal; The working frequency adjustment method based on the cache comprises the following steps: receiving an adjustment instruction for adjusting the working frequency of the processor; and disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment instruction, wherein in the process of adjusting the phase-locked loop, the cache receives the requests of the processing core and the connection architecture component and limits the requests to be sent to the memory controller so as to limit the processing core to call the memory.
  2. 2. The method of claim 1, wherein the cache and the memory controller are configured to control transmission of requests based on a predetermined credit mechanism, the credit mechanism comprising the cache allowing transmission of requests to the memory controller with a credit value; Before the disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment instruction, the method further comprises: acquiring and storing the current configuration of the cache to the credit mechanism; after the credit mechanism is closed, the cache is limited to transmit a request to the memory controller; And after disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment instruction, the method further comprises: and restoring the cached credit mechanism to the current configuration.
  3. 3. The cache-based operating frequency adjustment method of claim 2, wherein the processor further comprises a credit register, the credit register being coupled to the cache, the credit register being configured to record a credit value for the cache to send a request to the memory controller; the obtaining and saving the current configuration of the cache to the credit mechanism comprises obtaining and saving the current credit value recorded by the credit register; the credit mechanism for controlling the cache to close comprises the steps of adjusting the credit value recorded by the credit register to be 0; the restoring the cached credit mechanism to the current configuration includes adjusting the value recorded by the credit register to the current credit value.
  4. 4. The cache-based operating frequency adjustment method of claim 2, wherein the cache comprises a request buffer queue; after controlling the cache to close the credit mechanism, the method further comprises: And continuously receiving the requests sent by the processing core and the connection framework component through the cached request buffer queue.
  5. 5. The cache-based operating frequency adjustment method of claim 4, wherein after the request buffer queue through the cache continues to receive requests sent by the processing core and the connection architecture component, the method further comprises: And indicating the processing core to suspend request sending until the request buffer queue is full of requests.
  6. 6. The cache-based operating frequency adjustment method according to any one of claims 2-5, wherein the processor further comprises a reference clock source, the reference clock source being coupled to the processing core, the reference clock source being configured to output a reference clock; the adjustment instruction comprises a target working frequency required by the processor; The disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment instruction includes: switching a clock source of the processing core from the phase-locked loop to the reference clock source after controlling the cache to close the credit mechanism; Disabling the phase locked loop; Waiting until the phase-locked loop is unlocked, and adjusting the frequency of a clock signal output by the phase-locked loop to a target frequency, wherein the target frequency is a clock frequency for enabling the processor to work on the target working frequency; enabling the phase locked loop; Waiting until the phase-locked loop locks, switching the clock source of the processing core from the reference clock source back to the phase-locked loop.
  7. 7. The cache-based operating frequency adjustment method of claim 6, wherein after controlling the cache to close the credit mechanism, before switching the clock source of the processing core from the phase-locked loop to the reference clock source, the method further comprises: waiting for the processing core to enter an idle state, the idle state characterizing the processing core as being in a non-busy state.
  8. 8. The cache-based operating frequency adjustment method of claim 6, wherein the adjustment instruction characterizes a type of adjustment of the operating frequency of the processor as an up-conversion: Before said adjusting the frequency of the phase-locked loop output clock signal to a target frequency, the method further comprises: And increasing the working voltage of the processor to a voltage corresponding to the target working frequency.
  9. 9. The cache-based operating frequency adjustment method of claim 6, wherein the adjustment instruction characterizes a type of adjustment of the operating frequency of the processor as down-conversion; after the restoring the cached credit mechanism to the current configuration, the method further comprises: And reducing the working voltage of the processor to a voltage corresponding to the target working frequency.
  10. 10. A processor comprising a processor, a memory, and a control unit, characterized by comprising the following steps: The processor further comprises a phase-locked loop, wherein the phase-locked loop is connected with the processing core; the phase-locked loop is used for providing a clock signal for the processing core so that the processing core works based on the clock signal; the cache is configured to allow receipt of requests from the processing core and the connection architecture component and to restrict the requests from being sent to the memory controller during the phase locked loop being disabled and adjusted to restrict the processing core from invoking the memory; The phase locked loop is configured to be connected to a frequency modulation voltage regulation module configured to perform the cache-based operating frequency adjustment method according to any one of claims 1-9.
  11. 11. The processor of claim 10, further comprising the frequency and voltage modulation module.
  12. 12. The processor of claim 10, wherein the fm voltage regulator module is a module that is independent of the processor.
  13. 13. The processor according to claim 10 or 11, wherein the processor is a general-purpose graphics processor GPGPU.
  14. 14. An electronic device, comprising: The processor of any of claims 10-13.

Description

Working frequency adjusting method based on cache, processor and electronic equipment Technical Field The application relates to the field of integrated circuits, and particularly provides a working frequency adjusting method based on cache, a processor and electronic equipment. Background Currently, DVFS (Dynamic Voltage and Frequency Scaling, dynamically adjusting voltage and frequency) technology can dynamically adjust the operating frequency and power supply voltage of a processor according to the real-time load condition of the processor, so as to achieve the effects of reducing power consumption, improving the performance of the processor, and the like. The processing core in the processor controls the operating frequency by the clock signal provided by the phase-locked loop, so adjusting the operating frequency of the processor requires adjusting the phase-locked loop to change the clock signal output by the phase-locked loop. When the phase-locked loop is adjusted, the currently used clock source is required to be switched from the phase-locked loop to the reference clock, then the phase-locked loop is disabled to adjust the phase-locked loop in the disabled state, and the clock source is switched from the reference clock back to the phase-locked loop after the phase-locked loop is adjusted. Where the reference clock is typically a low frequency clock, for example, some reference clocks are 25MHz in frequency. And, the clock source may have a problem of 0 clock when switching between the phase locked loop and the reference clock, that is, a problem that the clock signal is 0 occurs in a short time. If a large number of tasks are issued to the processor by the upper layer application in the process of adjusting the working frequency, and operations such as calculation, data transmission, writing may be performed in each module of the processor, at this time, the frequency of the processor suddenly drops to be very low or even 0, which may cause abnormal problems such as system locking, data back pressure, data loss and the like of the processor. In some current solutions, the system clock input is turned off during frequency modulation, and turned on after the frequency modulation is completed, so as to solve the above problem. However, the task cannot be executed after the system clock is turned off, so that proper turn-off needs to be determined in advance, the task is controlled to be suspended, and the like, so that frequency modulation becomes more complex, and frequency modulation cannot be performed in time. In addition, when the phase-locked loop is disabled, the frequency change of the processing core may cause the working voltage of the processing core to drop, and in combination with the working voltage drop caused by application, the working voltage of the processor may not be in a normal range due to superposition of the two, so that the processor is abnormal. If the operating voltage of the processor needs to be satisfied, the voltage value of the operating voltage needs to be increased, which may degrade the performance of the processor. Disclosure of Invention In view of the foregoing, the present application is directed to a method for adjusting an operating frequency based on a cache, a processor, and an electronic device, so as to reduce the possibility of occurrence of an abnormal problem in the process of adjusting the operating frequency by the processor. In a first aspect, an embodiment of the present application provides a method for adjusting an operating frequency of a processor, where the processor includes a processing core, a connection architecture component, a cache, a memory controller, and a memory that are sequentially connected, the processor further includes a phase-locked loop, where the phase-locked loop is connected to the processing core, and the phase-locked loop is configured to provide a clock signal for the processing core to enable the processing core to operate based on the clock signal, and the method for adjusting an operating frequency based on the cache includes receiving an adjustment instruction for adjusting the operating frequency of the processor, disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment instruction, and in a process of adjusting the phase-locked loop, the cache receives a request from the processing core and the connection architecture component and limits the request from being sent to the memory controller to limit the processing core to call the memory. In the embodiment of the application, the cache can normally receive the requests from the processing core and the connection framework component in the process that the phase-locked loop of the processor is disabled and frequency-modulated, but all the requests are limited in the cache and cannot be sent to the memory controller, so that the processing core cannot call the memory and cannot execute the requests, and therefore, the processing