CN-122018634-A - Signal processing device, method and chip

CN122018634ACN 122018634 ACN122018634 ACN 122018634ACN-122018634-A

Abstract

The embodiment of the application provides a signal processing device, a signal processing method and a chip, which comprise a signal generating module, a counting module, a register module, a control module and an audio processing module, wherein the signal generating module is used for generating a first clock signal according to a first frequency control word, the counting module is used for counting the first number of the first clock signal in N preset clock cycles in a cyclic windowing mode and storing the first number into the register module, the control module is used for acquiring the first number from the register module, comparing the first number with the preset clock cycles to obtain a comparison result, and determining an adjustment strategy corresponding to the first frequency control word according to the comparison result so as to enable the input clock signal and the output clock signal of the audio processing module to keep a fixed phase, and the problem that the deviation of the output clock signal to one direction is larger and larger is avoided, so that the problem of Jie Jueduan sound is solved, and high-quality signal transmission of an audio system is realized.

Inventors

LU YILIN
ZHU SHUNYU
CHEN BOWEN

Assignees

昆腾微电子股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260127

Claims (12)

1. A signal processing device is characterized by comprising a signal generating module, a counting module, a register module, a control module and an audio processing module, wherein, The signal generation module is used for generating a first clock signal corresponding to a first frequency control word according to the first frequency control word; The counting module is used for counting a first number of the first clock signals in N preset clock periods by adopting a cyclic windowing mode, and storing the first number into the register module, wherein N is a natural number larger than 0; The control module is used for obtaining the first number from the register module, comparing the first number with the preset clock period to obtain a comparison result, and determining an adjustment strategy corresponding to the first frequency control word according to the comparison result so as to enable the input clock signal and the output clock signal of the audio processing module to keep fixed phases.
2. The signal processing device of claim 1, wherein the control module is further configured to determine a second number corresponding to the preset clock period based on the first number and the preset clock period.
3. The signal processing device of claim 2, wherein the control module is further configured to: Determining a preset clock number in the preset clock period; calculating the ratio of the first number to the preset clock number, and determining the ratio as a windowing sequence number; and determining the second quantity according to the windowing sequence numbers.
4. A signal processing apparatus according to claim 3, wherein said determining an adjustment strategy corresponding to said first frequency control word based on said comparison result comprises: calculating a difference between the first number and the second number; and determining an adjustment strategy corresponding to the first frequency control word according to the difference value.
5. The signal processing device of claim 4, wherein in the case where the preset clock period is from inside a chip, the determining an adjustment strategy corresponding to the first frequency control word according to the difference value comprises: If the difference is greater than 0, changing the first frequency control word into a second frequency control word, wherein the second frequency is smaller than the first frequency; And if the difference value is smaller than 0, changing the first frequency control word into a third frequency control word, wherein the third frequency is larger than the first frequency.
6. The signal processing device of claim 4, wherein in the case where the preset clock period is from outside the chip, the determining an adjustment strategy corresponding to the first frequency control word according to the difference value comprises: If the difference is greater than 0, changing the first frequency control word into a fourth frequency control word, wherein the fourth frequency is smaller than the first frequency; And if the difference value is smaller than 0, changing the first frequency control word into a fifth frequency control word, wherein the fifth frequency is larger than the first frequency.
7. The signal processing apparatus according to claim 4, further comprising a frequency dividing module, wherein the frequency dividing module is located between the signal generating module and the counting module, and the frequency dividing module is configured to perform frequency dividing processing on the first clock signal to obtain a frequency-divided signal.
8. A signal processing method, characterized by being applied to a signal processing apparatus according to any one of claims 1 to 7, the method comprising: generating a first clock signal corresponding to a first frequency control word according to the first frequency control word; counting a first number of the first clock signals in N preset clock cycles by adopting a cyclic windowing mode, and storing the first number into a register module; The first quantity is obtained from the register module, and the first quantity is compared with the preset clock period to obtain a comparison result; and determining an adjustment strategy corresponding to the first frequency control word according to the comparison result so as to keep the input clock signal and the output clock signal of the audio processing module in fixed phases.
9. The method of claim 8, wherein counting the first number of the first clock signals in N preset clock cycles by means of cyclic windowing comprises: if n=1, taking the number of the first clock signals in the first preset clock period as a first number; if N is greater than 1, taking the sum of the numbers of the first clock signals in the first N preset clock cycles as the first number.
10. The method of claim 8, wherein the obtaining the first number, comparing the first number with the predetermined clock period, and obtaining a comparison result comprises: Determining a preset clock number in the preset clock period; calculating the ratio of the first number to the preset clock number, and determining the ratio as a windowing sequence number; Determining a second number according to the windowing sequence number; And comparing the first number with the second number to obtain a comparison result.
11. The method of claim 10, wherein the determining an adjustment strategy corresponding to the first frequency control word based on the comparison result comprises: calculating a difference between the first number and the second number; and determining an adjustment strategy corresponding to the first frequency control word according to the difference value.
12. A chip comprising a signal processing device according to any one of claims 1-7.

Description

Signal processing device, method and chip Technical Field The present application relates to the field of data processing technologies, and in particular, to a signal processing device, a signal processing method, and a chip. Background With the continuous development of various electronic technologies, the requirements on audio are higher and higher, but for an audio system, if the temperature of the chip itself changes or is externally interfered, or is interfered by clocks sent by other devices, the clock of the audio chip itself is affected, and further the transmission of audio data is affected, and for a user, the phenomenon of discontinuous audio, namely the phenomenon of sound interruption, is generated, so that the phenomenon of sound interruption needs to be reduced. Disclosure of Invention The application aims to provide a signal processing device, a method and a chip, and the device comprises a signal generating module, a counting module, a register module, a control module and an audio processing module, wherein the signal generating module is used for generating a first clock signal corresponding to a first frequency control word according to the first frequency control word, the counting module is used for counting the first number of the first clock signal in N preset clock periods in a cyclic windowing mode and storing the first number into the register module, N is a natural number larger than 0, the control module is used for acquiring the first number from the register module, comparing the first number with the preset clock period to obtain a comparison result, determining an adjustment strategy corresponding to the first frequency control word according to the comparison result, so that the input clock signal and the output clock signal of the audio processing module keep a fixed phase, the application is used for tracking the first number of the first clock signal in N preset clock periods in a cyclic windowing mode, the clock signal generating module can acquire the clock signal in a stable phase range relative to the clock signal when the number of the preset clock signal is not changed in the preset clock period, the clock signal is always compared with the preset clock period, and the clock signal is not more than the preset clock period, the problem of the clock signal is always acquired in the clock signal is not more than the preset clock period, and the clock signal is always compared in the preset clock period, thereby realizing high-quality signal transmission of the audio system. In a first aspect, some embodiments of the present application provide a signal processing apparatus comprising a signal generating module, a counting module, a register module, a control module, and an audio processing module, wherein, The signal generation module is used for generating a first clock signal corresponding to a first frequency control word according to the first frequency control word; The counting module is used for counting a first number of the first clock signals in N preset clock periods by adopting a cyclic windowing mode, and storing the first number into the register module, wherein N is a natural number larger than 0; The control module is used for obtaining the first number from the register module, comparing the first number with the preset clock period to obtain a comparison result, and determining an adjustment strategy corresponding to the first frequency control word according to the comparison result so as to enable the input clock signal and the output clock signal of the audio processing module to keep fixed phases. According to some embodiments of the application, the clock signals generated by the signal generation module are tracked in real time through the counting module, if the external environment is changed, the control module compares the number of clock signals acquired in a preset clock period with the number of clock signals in the preset clock period, and adjusts control words corresponding to the clock signals according to the comparison result, so that the input clock signals and the output clock signals of the audio processing module keep fixed phases, namely the phases of the output clock signals relative to the input clock signals are always stable in a preset range, the problem that the deviation of the output clock signals from one direction is larger and larger is avoided, and the problem of sound interruption is avoided, thereby realizing high-quality signal transmission of the audio system. Optionally, the control module is further configured to determine, according to the first number and the preset clock period, a second number corresponding to the preset clock period. Optionally, the control module is further configured to: Determining a preset clock number in the preset clock period; calculating the ratio of the first number to the preset clock number, and determining the ratio as a windowing sequence number; and determining the second qu