CN-122018665-A - Power consumption control circuit, chip and electronic equipment

CN122018665ACN 122018665 ACN122018665 ACN 122018665ACN-122018665-A

Abstract

The embodiment of the application provides a power consumption control circuit, a chip and electronic equipment, wherein the circuit comprises a first storage circuit, a state identification circuit and a clock control circuit, the state identification circuit is connected to a transmission channel, the first storage circuit is respectively connected to the state identification circuit and the clock control circuit, the state identification circuit is used for identifying the state of the transmission channel in each clock period and storing the state into the first storage circuit, the first storage circuit is used for storing the states of a plurality of clock periods, and the clock control circuit is used for controlling the clock frequency of the transmission channel according to the states in the first storage circuit. The application sets power consumption control circuit for different transmission channels, and adjusts the clock frequency of the transmission channels in a self-adaptive way according to the states of each transmission channel in a plurality of time periods. Therefore, the power consumption generated by the clock of each transmission channel can be reduced as much as possible, and the power consumption of the whole semiconductor chip can be effectively reduced.

Inventors

ZHANG CHEN
LIU YIMIN
WANG HUANDONG

Assignees

龙芯中科技术股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260113

Claims (12)

1. A power consumption control circuit, comprising: the system comprises a first storage circuit, a state identification circuit and a clock control circuit, wherein the state identification circuit is connected to a transmission channel, and the first storage circuit is respectively connected to the state identification circuit and the clock control circuit; the state identification circuit is used for identifying the state of the transmission channel in each clock cycle and storing the state into the first storage circuit, and the first storage circuit is used for storing the states of a plurality of clock cycles; the clock control circuit is used for controlling the clock frequency of the transmission channel according to a plurality of states in the first storage circuit.
2. The power consumption control circuit according to claim 1, wherein the state recognition circuit includes an input count circuit, an output count circuit, and a state output circuit, the output terminal of the input count circuit and the output terminal of the output count circuit being connected to the two input terminals of the state output circuit, respectively; The input counting circuit is used for counting the input data quantity of the transmission channel in each clock period; The output counting circuit is used for counting the output data quantity of the transmission channel in each clock period; The state output circuit is used for determining the state of the transmission channel in the clock period according to the input data quantity and the output data quantity.
3. The power consumption control circuit according to claim 2, wherein the state output circuit includes a subtracting circuit and a first comparing circuit, an output terminal of the subtracting circuit being connected to one input terminal of the first comparing circuit, the other input terminal of the first comparing circuit corresponding to a first threshold value; the subtracting circuit is used for calculating the difference value between the input data quantity and the output data quantity; the first comparison circuit is used for comparing the difference value with the first threshold value to obtain the state of the transmitted channel in the clock period.
4. The power consumption control circuit according to any one of claims 1 to 3, wherein the clock control circuit comprises a state counting circuit and a dynamic clock circuit, an input terminal of the state counting circuit being connected to the first storage circuit, an output terminal of the state counting circuit being connected to the dynamic clock circuit; the state counting circuit is used for counting the number of target values in the first storage circuit to obtain the number of target states, and the target values indicate that the transmission channel is in a busy state; the dynamic clock circuit is used for generating a dynamic clock signal according to the target state quantity, and the clock frequency of the dynamic clock signal is related to the target state quantity.
5. The power consumption control circuit according to claim 4, wherein the transmission channel corresponds to a clock generation circuit, the dynamic clock circuit comprises a clock generation circuit, a control signal generation circuit and a frequency adjustment circuit, and an output end of the clock generation circuit and an output end of the control signal generation circuit are respectively connected to two input ends of the frequency adjustment circuit; The clock generation circuit is used for generating a basic clock signal with basic clock frequency; the control signal generation circuit is used for generating a first control signal according to the target state quantity; The frequency adjusting circuit is used for adjusting the clock frequency of the basic clock signal according to the first control signal to obtain a dynamic clock signal.
6. The power consumption control circuit according to claim 5, wherein the control signal generation circuit includes a second comparison circuit having a plurality of inputs respectively connected to the target state number and a second threshold; The second comparison circuit is used for comparing the target state quantity with the second threshold value to obtain the first control signal.
7. The power consumption control circuit of claim 6, wherein the second comparison circuit comprises at least two second comparison sub-circuits, different ones of the second comparison circuits corresponding to different ones of the second thresholds.
8. The power consumption control circuit according to claim 7, wherein the frequency adjustment circuit includes a plurality of frequency adjustment sub-circuits, each of the frequency adjustment sub-circuits being connected to one of the second comparison sub-circuits; The frequency adjustment sub-circuit is used for carrying out frequency adjustment on the basic clock signal through preset frequency modulation parameters to obtain a dynamic clock signal, and different frequency adjustment sub-circuits correspond to different preset frequency modulation parameters.
9. The power consumption control circuit of claim 8, wherein the dynamic clock circuit further comprises a down-conversion control circuit coupled to the state count circuit, the control signal generation circuit, and the frequency adjustment circuit, the down-conversion control circuit configured to control the currently operating frequency adjustment sub-circuit to continue to operate for a target period of time based on the target number of states when the first control signal indicates the down-conversion of the dynamic clock signal, the target period of time being related to the target number of states.
10. A power consumption control circuit according to any one of claims 1 to 3, wherein the first storage circuit is a shift register for shifting upon receipt of a state of one of the clock cycles to store the state to a most significant bit or a least significant bit.
11. A semiconductor chip comprising a plurality of power consumption control circuits according to any one of claims 1 to 10, each for clock frequency control of one transmission channel, each for data transmission between two routers.
12. An electronic device comprising the semiconductor chip of claim 11.

Description

Power consumption control circuit, chip and electronic equipment Technical Field The present application relates to the field of semiconductor chips, and in particular, to a power consumption control circuit, a chip, and an electronic device. Background Semiconductor chips are an important component in various electronic devices, and their power consumption affects the endurance of the electronic device. Therefore, power consumption of the semiconductor chip is an important factor to be considered in designing the semiconductor chip. In the prior art, dynamic frequency modulation and voltage regulation (Dynamic Voltage and Frequency Scaling, DVFS) technology can be used to reduce the power consumption of the semiconductor chip. The voltage and the current are reduced simultaneously when the circuit in the semiconductor chip does not need to run in full load so as to reduce the static power consumption and the dynamic power consumption of the circuit, and the voltage of the circuit is reduced under the condition that the circuit does not work, and at the moment, the clock is completely turned off so as to reduce the static power consumption of the circuit. However, the above scheme still has a problem of high power consumption of the semiconductor chip. Disclosure of Invention In view of the above, embodiments of the present application have been made to provide a power consumption control circuit that overcomes or at least partially solves the above-mentioned problems to reduce power consumption of a semiconductor chip. Correspondingly, the embodiment of the application also provides a semiconductor chip and electronic equipment, which are used for ensuring the realization and application of the power consumption control circuit. In order to solve the above-mentioned problems, an embodiment of the present application discloses a power consumption control circuit, including: A first memory circuit, a state identification circuit and a clock control circuit, wherein the state identification circuit is connected to a transmission channel, the first storage circuit is respectively connected to the state identification circuit and the clock control circuit; the state identification circuit is used for identifying the state of the transmission channel in each clock cycle and storing the state into the first storage circuit, and the first storage circuit is used for storing the states of a plurality of clock cycles; the clock control circuit is used for controlling the clock frequency of the transmission channel according to a plurality of states in the first storage circuit. The state identification circuit comprises an input counting circuit, an output counting circuit and a state output circuit, wherein the output end of the input counting circuit and the output end of the output counting circuit are respectively connected to two input ends of the state output circuit, the input counting circuit is used for counting the input data quantity of the transmission channel in each clock cycle, the output counting circuit is used for counting the output data quantity of the transmission channel in each clock cycle, and the state output circuit is used for determining the state of the transmission channel in the clock cycle according to the input data quantity and the output data quantity. The state output circuit comprises a subtracting circuit and a first comparing circuit, wherein the output end of the subtracting circuit is connected to one input end of the first comparing circuit, the other input end of the first comparing circuit corresponds to a first threshold value, the subtracting circuit is used for calculating the difference value between the input data quantity and the output data quantity, and the first comparing circuit is used for comparing the difference value with the first threshold value to obtain the state of the transmitted channel in the clock period. The clock control circuit comprises a state counting circuit and a dynamic clock circuit, wherein the input end of the state counting circuit is connected to the first storage circuit, the output end of the state counting circuit is connected to the dynamic clock circuit, the state counting circuit is used for counting the number of target values in the first storage circuit to obtain the number of target states, the target values indicate that the transmission channel is in a busy state, the dynamic clock circuit is used for generating a dynamic clock signal according to the number of target states, and the clock frequency of the dynamic clock signal is related to the number of target states. Optionally, the transmission channel is correspondingly provided with a clock generating circuit, the dynamic clock circuit comprises a clock generating circuit, a control signal generating circuit and a frequency adjusting circuit, the output end of the clock generating circuit and the output end of the control signal generating circuit are respectively conne