CN-122018774-A - Memory system and method for operating in-memory computation

Abstract

The invention provides a memory system and an operation method of in-memory calculation. The memory system comprises a memory controller, a memory, a first filter and a second filter. The storage controller is used for receiving a first stage result. The memory is used for performing in-memory operation on the first stage result to generate a second stage result. The first stage filter is used for filtering the second stage result to generate a third stage result. The second filter is used for filtering the third stage result to generate a fourth stage result. The memory system outputs the fourth stage result when a number of the plurality of data results in the third stage result is greater than a preset threshold number, and outputs the third stage result when the number of the data results in the third stage result is less than or equal to the preset threshold number.

Inventors

• LIN BAIRONG
• HU HANWEN

Assignees

• 旺宏电子股份有限公司

Dates

Publication Date

20260512

Application Date

20250418

Priority Date

20250401

Claims (10)

1. 1. A memory system, comprising: a storage controller for receiving a first stage result; A memory for performing in-memory operation on the first stage result to generate a second stage result; A first stage filter for filtering the second stage result to generate a third stage result, and A second filter for filtering the third stage result to generate a fourth stage result, Wherein the memory system outputs the fourth stage result when a number of the plurality of data results in the third stage result is greater than a predetermined threshold number, and When the number of the data results in the third stage result is less than or equal to the preset threshold number, the memory system outputs the third stage result.
2. 2. The memory system of claim 1, wherein The storage controller is used for outputting the third stage result or the fourth stage result to a processing device.
3. 3. The memory system of claim 2, wherein the second filter is further configured to sort the data results in the third stage result according to a plurality of data values of the data results in the third stage result, and select N1 data results from the third stage result as the fourth stage result, and N1 is a positive integer less than or equal to the predetermined threshold number.
4. 4. The memory system of claim 3, wherein N1 is determined based on a verification index corresponding to a first test data set.
5. 5. The memory system of claim 4, wherein the verification index is accuracy.
6. 6. The memory system of claim 5, wherein the first stage filter is further configured to filter the first test data set to generate a second test data set, The second filter is also configured to filter the second test data set to generate a third test data set, an The memory system is used for adjusting N1 according to a first accuracy rate corresponding to the second test data set and a second accuracy rate corresponding to the third test data set.
7. 7. The memory system of claim 6, wherein the memory system is further configured to compare the second accuracy rate to a predetermined accuracy rate, When the second accuracy is less than the preset accuracy, the memory system increases N1, and When the second accuracy rate is greater than or equal to the preset accuracy rate, the memory system determines N1.
8. 8. A method of operation of in-memory computing, comprising: Filtering a first stage result by a first stage filter to generate a second stage result; comparing the number of data results in the second stage result with a preset threshold number, and When the number of the data results in the second stage results is larger than the preset threshold number, the second stage results are filtered by a second stage filter to generate a third stage result.
9. 9. The method of claim 8, wherein the first stage filter is configured to set a threshold value to filter the first stage result.
10. 10. The method of claim 9, wherein filtering the second stage results to produce the third stage results comprises: ordering the data results in the second stage result according to the data values of the data results in the second stage result by the second stage filter, and Selecting N1 data results from the second stage results as the third stage results by the second stage filter, Wherein N1 is a positive integer less than or equal to the predetermined threshold number.

Description

Memory system and method for operating in-memory computation Technical Field The present invention relates to a memory technology, and more particularly, to a memory system and a method for operating an in-memory computing device. Background Artificial Intelligence (AI) has recently become a very effective solution in many classification tasks. The key operation of AI is that it contains a large number of input feature maps and weights to perform multiply-accumulate (MAC) operations. However, current Von Neumann (Von Neumann) architectures based on Complementary Metal Oxide Semiconductors (CMOS), i.e. Central Processing Units (CPUs) or image processing units (GPUs) are equipped with external memories, suffer from input/output bottlenecks and inefficient MAC operation flows. Therefore, how to solve the above-mentioned problems is an important problem in the art. Disclosure of Invention Embodiments of the present invention include a memory system. The memory system includes a memory controller and a memory. The storage controller is used for receiving a first stage result. The memory is used for performing in-memory operation on the first stage result to generate a second stage result. The memory device includes a first filter and a second filter. The first stage filter is used for filtering the second stage result to generate a third stage result. The second filter is used for filtering the third stage result to generate a fourth stage result. The memory system outputs the fourth stage result when a number of the plurality of data results in the third stage result is greater than a preset threshold number, and outputs the third stage result when the number of the data results in the third stage result is less than or equal to the preset threshold number. The embodiment of the invention comprises an operation method of in-memory calculation. The operation method comprises the steps of filtering a first stage result through a first stage filter to generate a second stage result, comparing the number of data results in the second stage result with a preset threshold number, and filtering the second stage result through a second stage filter to generate a third stage result when the number of data results in the second stage result is larger than the preset threshold number. Drawings FIG. 1 is a schematic diagram illustrating an operation method of in-memory computing according to some embodiments of the invention. FIG. 2 is a schematic diagram of a memory system according to some embodiments of the invention. FIG. 3 is a schematic diagram of accuracy of a test dataset according to some embodiments of the present invention. Reference numerals illustrate: 100 method of operation OP11 to OP17 operation DS 1-DS 5 stage results DS6 final filtration results 200 System 210 Processing device 220 Storage system 221 Storage controller 222 Memory MC 1-MC 4 memory chip FLF 1-FLF 4 first stage filter SLF1 second stage Filter AC1, AC2 accuracy TDS1, TDS31, TDS32 test data set Detailed Description Herein, when an element is referred to as being "connected" or "coupled," it can be referred to as being "electrically connected" or "electrically coupled. "connected" or "coupled" may also be used to indicate that two or more elements are in co-operation or interaction with each other. In addition, although the terms "first," "second," and the like may be used herein to describe various elements, this term is merely intended to distinguish between elements or operations described in the same technical term. Unless the context clearly indicates otherwise, the terms are not specifically intended or implied to be order or cis-ient nor intended to limit the invention. Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well as "at least one" unless the context clearly indicates otherwise. "or" means "and/or" are provided. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions,