CN-122018777-A - Storage device and method for completion

Abstract

A storage device and method for completion. A storage device configured for connection to a host device includes a non-volatile memory and a storage controller configured to receive a write command for the non-volatile memory from the host device and to control programming write data corresponding to the write command in the non-volatile memory. The memory controller may be configured to transmit a completion signal indicating completion of the write command to the host device based on at least one of programming state information indicating a programming state of the write command or device state information of the memory device.

Inventors

• Zhao Zhenzai
• Jin Zhuanglv
• JIN RENSHOU
• Pu Zhenyong
• YU XIANGYU

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20251111

Priority Date

20241112

Claims (20)

1. 1. A storage device, the storage device comprising: Nonvolatile memory, and A memory controller configured to receive a write command for the nonvolatile memory from a host device, and control programming write data corresponding to the write command in the nonvolatile memory, Wherein: The memory controller is configured to transmit a completion signal indicating completion of the write command to the host device based on at least one of programming state information indicating a programming state of the write command or device state information of the memory device.
2. 2. The storage device of claim 1, wherein: the programming state indicates a single processing stage among a plurality of processing stages of the write command.
3. 3. The storage device of claim 2, wherein: The plurality of processing stages includes at least one of an extraction stage of the write command, a buffering stage of the write data, a stage for transferring the write data for a pre-program operation to the non-volatile memory, a pre-program stage, a stage for transferring the write data for a re-program operation to the non-volatile memory, or a re-program stage.
4. 4. The storage device of claim 1, further comprising: A buffer memory configured to buffer the write data, Wherein: The memory controller is configured to backup buffered write data to the non-volatile memory when a sudden power-off SPO is detected from the memory device.
5. 5. The storage device of claim 4, wherein: The programming state indicates a single processing sequence among a plurality of processing sequences, each of the plurality of processing sequences including a processing stage of the write command, and The plurality of processing sequences are defined based on a backup size required for each of the plurality of processing sequences.
6. 6. The storage device of claim 5, wherein: The memory controller is configured to set a single processing sequence having the backup size equal to a size of the buffer memory among the plurality of processing sequences as the completed transmission time of the write command.
7. 7. The storage device of claim 1, wherein: The memory controller is configured to transmit the completion signal to the host device when the programming state matches a transmission time set for the completion of the write command.
8. 8. The storage device of claim 5, wherein: the memory controller is configured to omit backup for the single processing sequence when the single processing sequence matches a transmission time set for the completion of the write command.
9. 9. The storage device of claim 1, wherein: The device state information includes at least one of a queue depth of a command queue for the write command at any time or a size of the write command.
10. 10. The storage device of claim 9, wherein: the memory controller is configured to: comparing a first data size defined based on at least one of the queue depth of the command queue or the size of the write command with a second data size required for each of a plurality of processing sequences of the write command, and The transmission time of the completion of the write command is set based on one or more processing sequences having the second data size smaller than or equal to the first data size among the plurality of processing sequences.
11. 11. The storage device of claim 1, wherein: The programming state indicates the number of lanes activated in each processing sequence of the write command.
12. 12. A method of operating a memory controller of a memory device, the memory device comprising a non-volatile memory, the method comprising: Receiving a write command from a host device; obtaining programming state information indicating a programming state of the write command and device state information of the memory device, and A completion signal indicating completion of the write command is sent to the host device based on at least one of the programming status information or the device status information.
13. 13. The method according to claim 12, wherein: the programming state indicates a single processing stage among a plurality of processing stages of the write command, an The plurality of processing stages includes at least one of an extraction stage of the write command, a buffering stage of write data, a stage for transferring the write data for a pre-program operation to the non-volatile memory, a pre-program stage, a stage for transferring the write data for a re-program operation to the non-volatile memory, or a re-program stage.
14. 14. The method of claim 12, further comprising: selecting a single processing sequence having a backup size equal to the size of the buffer memory from among processing sequences including a plurality of processing stages of the write command, and The selected single processing sequence is set to the transmission time for the completion of the write command.
15. 15. The method of claim 12, further comprising: checking whether the programming state matches a send time set for the completion of the write command, Wherein: the sending of the completion signal to the host device is performed when the programming state matches the sending time.
16. 16. The method of claim 15, further comprising: when a single processing sequence indicated by the program state matches the transmission time, backup for the single processing sequence is omitted.
17. 17. The method according to claim 12, wherein: The device state information includes at least one of a queue depth of a command queue for the write command at any time or a size of the write command.
18. 18. The method of claim 17, further comprising: comparing a first data size defined based on at least one of the queue depth of the command queue or the size of the write command with a second data size required for each of a plurality of processing sequences of the write command, and The transmission time of the completion of the write command is set based on one or more processing sequences having the second data size smaller than or equal to the first data size among the plurality of processing sequences.
19. 19. A storage device, the storage device comprising: a nonvolatile memory; A memory controller configured to receive a write command for the nonvolatile memory from a host device and control programming write data corresponding to the write command in the nonvolatile memory; a buffer memory configured to buffer the write data, and A power-off protection PLP circuit configured to detect a sudden power-off SPO from the storage device, Wherein the storage controller is configured to: transmitting a completion signal indicating completion of the write command to the host device based on at least one of programming state information indicating a programming state of the write command or device state information of the storage device, and When the SPO is detected before the completion signal is sent to the host device, backing up buffered write data to the non-volatile memory is omitted.
20. 20. The storage device of claim 19, wherein: The memory controller is configured to transmit the completion signal to the host device when the programming state matches a transmission time set for the completion of the write command.

Description

Storage device and method for completion Cross Reference to Related Applications The present application claims priority from korean patent application No.10-2024-0160450 filed in the korean intellectual property office on day 11 and 12 of 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field Example embodiments relate generally to a storage device and method for completion. Background The storage device stores data under control of a host device such as a computer, smart phone or tablet. Most storage devices are powered by an external power source. However, the storage device is vulnerable to damage, including data loss, due to a failure of an external power source or a power failure such as a Sudden Power Outage (SPO). To address the above power-related issues, the storage device may support power-off protection (power loss protection, PLP). PLP enables a storage device to backup (or dump) data stored in a buffer memory (or cache memory) to a non-volatile memory in the event of a power outage. The storage device may execute the command completion on the write command by buffering the data in the buffer memory and then sending the completion of the write command to the host. In the event of a power outage after completion of the execution command, the storage device should fully guarantee a backup of the data. Thus, it is considered to reduce the standby amount by adjusting the completion time. Disclosure of Invention Example embodiments provide a storage device capable of reducing a backup amount by setting a completion transmission time and a method for completion. According to an example embodiment, a memory device includes a nonvolatile memory and a memory controller configured to receive a write command for the nonvolatile memory from a host device and control programming write data corresponding to the write command in the nonvolatile memory. The memory controller may be configured to transmit completion of the write command to the host device based on at least one of program state information indicating a program state (program state) of the write command or device state information of the memory device. According to an example embodiment, a method of a storage device includes receiving a write command from a host device, obtaining programming state information indicating a programming state of the write command and device state information of the storage device, and transmitting completion of the write command to the host device based on at least one of the programming state information or the device state information. According to an example embodiment, a memory device includes a non-volatile memory, a memory controller configured to receive a write command for the non-volatile memory from a host device and to control programming write data corresponding to the write command in the non-volatile memory, a buffer memory configured to buffer the write data, and a power-off protection (PLP) circuit configured to detect a Sudden Power Outage (SPO) from the memory device. The memory controller may be further configured to send completion of the write command to the host device based on at least one of programming state information indicating a programming state of the write command or device state information of the memory device, and omit backing up buffered write data to the nonvolatile memory when the SPO is detected before sending the completion to the host device. Drawings The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters (when used) designate corresponding elements throughout the several views, and in which: FIG. 1 is a block diagram illustrating at least a portion of a storage system according to an example embodiment; FIG. 2 is a block diagram illustrating an example of the memory controller of FIG. 1 in accordance with an example embodiment; FIG. 3 is a block diagram of the non-volatile memory of FIG. 1 according to an example embodiment; FIG. 4 is a circuit diagram illustrating an example of a memory block within the memory cell array of FIG. 3 according to an example embodiment; FIG. 5 is a diagram illustrating data states before and after a program operation and a reprogramming operation according to an example embodiment; FIG. 6 is a timing diagram illustrating a backup operation in the event of a Sudden Power Off (SPO); fig. 7 is a timing diagram illustrating an operation of setting a completion transmission time within a preprogrammed state according to an example embodiment; FIG. 8 is a timing diagram illustrating an operation of setting a completion transmit time within a reprogramming state according to an example embodiment; Fig. 9 is a timing chart showing an operation of setting a completion transmission time according to an example embodiment; fig. 10 is