CN-122018786-A - Data writing method, data writing system, device and storage medium

CN122018786ACN 122018786 ACN122018786 ACN 122018786ACN-122018786-A

Abstract

The disclosure provides a data writing method, a data writing system, equipment and a storage medium, and relates to the technical field of data processing. The method comprises the steps of receiving a first data writing request of a first-level cache unit through a first data distribution unit, writing first-level cache data corresponding to the first data writing request into an on-chip storage unit through the first data distribution unit, receiving a second data writing request of a non-first-level cache unit through a second data distribution unit, and writing non-first-level cache data corresponding to the second data writing request into the on-chip storage unit through the second data distribution unit. Therefore, the writing paths of the first-level cache data and the non-first-level cache data are separated, writing competition between the first-level cache data and the non-first-level cache data is reduced, delay of writing the first-level cache data into the on-chip storage unit is reduced, writing efficiency of the first-level cache data is improved, and therefore data writing performance of the on-chip storage unit is improved.

Inventors

Request for anonymity

Assignees

摩尔线程智能科技(北京)股份有限公司

Dates

Publication Date: 20260512
Application Date: 20251226

Claims (17)

1. A data writing method, characterized by being applied to a data writing system, the data writing system including a first data distribution unit and a second data distribution unit, the first data distribution unit being a dedicated distribution unit for processing first-level cache data, the second data distribution unit being a general distribution unit for processing non-first-level cache data, the method comprising: Receiving a first data writing request of a first-level cache unit through the first data distribution unit, and writing first-level cache data corresponding to the first data writing request into an on-chip storage unit through the first data distribution unit; And receiving a second data writing request of the non-primary cache unit through the second data distribution unit, and writing non-primary cache data corresponding to the second data writing request into the on-chip storage unit through the second data distribution unit.
2. The method of claim 1, wherein the first data distribution unit is configured to write the first level cache data to the on-chip memory unit bypassing a preset arbitration process flow; The second data distribution unit is configured to write the non-primary cache data into the on-chip storage unit through the preset arbitration processing flow.
3. The method according to claim 1, wherein the writing, by the first data distribution unit, the first level cache data corresponding to the first data write request to the on-chip storage unit includes: Acquiring the first-level cache data through the first data distribution unit, wherein the first-level cache data comprises a plurality of target data; sequentially storing the plurality of target data into a data buffer in the first data distribution unit according to the acquisition sequence of the plurality of target data through the first data distribution unit; And writing the plurality of target data in the data buffer into the on-chip storage unit through the first data distribution unit.
4. The method of claim 3, wherein the obtaining, by the first data distribution unit, the first level cache data comprises: Acquiring the residual buffer depth of the data buffer through the first data distribution unit; when the residual buffer depth is greater than or equal to a preset depth threshold value, acquiring first-level buffer data of which the residual buffer depth corresponds to the first-level buffer data by the first data distribution unit; And when the residual buffer depth is smaller than the preset depth threshold value, controlling the first data distribution unit to stop acquiring the first-level buffer data.
5. The method of claim 3, wherein the writing the plurality of target data in the data buffer to the on-chip memory unit comprises: For each target data in the data buffer, determining a target storage block corresponding to the target data in the on-chip storage unit, wherein the on-chip storage unit comprises a plurality of storage blocks for storing data, and the target storage block is a storage block for storing the target data in the on-chip storage unit; Determining at least one target data to be stored corresponding to each target storage block, wherein the target data to be stored is the target data which is requested to be written into the target storage block in the data buffer; And for each target storage block, writing each target data to be stored corresponding to the target storage block into the target storage block in the on-chip storage unit in sequence according to the storage sequence of each target data to be stored corresponding to the target storage block in the data buffer.
6. The method of claim 5, wherein determining, in the on-chip memory unit, a target memory block corresponding to the target data comprises: acquiring a target storage address of the target data in the on-chip storage unit from the first data writing request; and determining a storage block corresponding to the target storage address based on the mapping relation between the target storage address and the storage block in the on-chip storage unit, and determining the storage block corresponding to the target storage address in the on-chip storage unit as the target storage block corresponding to the target data.
7. The method according to claim 5, wherein for each of the target memory blocks, writing each target data to be stored corresponding to the target memory block into the target memory block in the on-chip memory unit in sequence according to the storage order of each target data to be stored corresponding to the target memory block in the data buffer, includes: constructing a pointer queue corresponding to each target storage block based on target data to be stored corresponding to the target storage block; Based on pointer queues corresponding to the target storage blocks, for each target storage block, sequentially writing each target data to be stored corresponding to the target storage block into the target storage blocks in the on-chip storage unit according to the storage sequence of each target data to be stored corresponding to the target storage block in the data buffer; The pointer queue comprises pointer data of each target data to be stored, which corresponds to the target storage block, the arrangement sequence of the pointer data in the pointer queue is the same as the storage sequence of the target data to be stored in the data buffer, the pointer data comprises a storage address and a storage sequence number of the target data to be stored in the data buffer, and the size of the storage sequence number is inversely related to the storage duration of the target data to be stored in the data buffer.
8. The method of claim 7, wherein the constructing a pointer queue corresponding to the target storage block based on each target data to be stored corresponding to the target storage block comprises: Acquiring a storage address and a storage sequence number of each target data to be stored in the data buffer; Constructing pointer data of the target data to be stored according to the storage address and the storage sequence number of the target data to be stored in the data buffer aiming at each target data to be stored; and ordering the pointer data of each target data to be stored according to the storage sequence of each target data to be stored in the data buffer, so as to obtain a pointer queue corresponding to the target storage block.
9. The method according to claim 7, wherein the writing, for each of the target memory blocks, each target data to be stored corresponding to the target memory block into the target memory block in the on-chip memory unit in sequence according to the storage order of each target data to be stored corresponding to the target memory block in the data buffer based on the pointer queue corresponding to each target memory block, includes: reading first pointer data in each pointer queue, and sequencing storage sequence numbers in each first pointer data from small to large to obtain a target sequence; starting from the first storage sequence number of the target sequence, taking the first storage sequence number as a target storage sequence number; Writing target data to be stored corresponding to the target storage sequence number into a target storage block corresponding to the target storage sequence number; Responding to the fact that target data to be stored corresponding to the target storage sequence numbers are successfully written into target storage blocks corresponding to the target storage sequence numbers, taking the storage sequence numbers larger than the target storage sequence numbers as the storage sequence numbers to be processed, and respectively moving the storage addresses of the target data to be stored corresponding to the storage sequence numbers to be processed in the data buffer to one bit in a target direction to obtain updated target data to be stored corresponding to each target storage block, wherein the target direction is the direction of the storage addresses of the target data to be stored corresponding to the target storage sequence numbers; deleting pointer data corresponding to the target storage sequence number, and respectively subtracting one of the storage sequence numbers to be processed in each pointer queue to obtain updated pointer queues; and re-executing the steps of reading the first pointer data in each pointer queue and the later steps based on the updated target data to be stored and the updated pointer queues.
10. The method of claim 9, wherein writing the target data to be stored corresponding to the target storage sequence number into the target storage block corresponding to the target storage sequence number comprises: Identifying whether a target storage block corresponding to the target storage sequence number meets a write-once condition of target data to be stored corresponding to the target storage sequence number; When the target storage block corresponding to the target storage sequence number does not meet the write-once condition, suspending processing the data to be stored corresponding to the target storage sequence number, taking the next storage sequence number of the first storage sequence number in the target sequence as the target storage sequence number, and re-executing the steps of identifying whether the target storage block corresponding to the target storage sequence number meets the write-once condition of the data to be stored corresponding to the target storage sequence number and the following steps; and when the target storage block corresponding to the target storage sequence number meets the write-once condition, writing target data to be stored corresponding to the target storage sequence number into the target storage block corresponding to the target storage sequence number.
11. The method according to claim 10, wherein the method further comprises: And stopping writing data into the on-chip storage unit when the target storage blocks corresponding to the storage sequence numbers in the target sequence do not meet the write-once conditions corresponding to the storage sequence numbers.
12. The method of claim 10, wherein the identifying whether the target storage block corresponding to the storage sequence number satisfies a write-once condition of target data to be stored corresponding to the storage sequence number comprises: Acquiring the current writing state of a target storage block corresponding to the storage sequence number in the on-chip storage unit; When the current writing state of the target storage block is a writable state, identifying whether target storage units with target number exist in the target storage block, wherein the target number is the number of target storage units to be stored for target data requests corresponding to the storage sequence number, and the target storage units are storage units in the target storage block, which are currently allowed to write data; when the target storage units with the target number exist in the target storage blocks, determining that the target storage blocks corresponding to the storage sequence numbers meet the write-once condition; And when the current writing state of the target storage block is a non-writable state or the target storage block does not have the target number of target storage units, determining that the target storage block corresponding to the storage sequence number does not meet the write-once condition.
13. The method of claim 12, wherein the obtaining the current writing state of the target memory block corresponding to the memory sequence number in the on-chip memory unit includes: acquiring a write enabling signal of a target storage block corresponding to the storage sequence number from the on-chip storage unit; when the write enabling signal of the target storage block is a first target enabling signal, determining that the current writing state of the target storage block is a writable state, wherein the first target enabling signal is an enabling signal representing that the target storage block is currently allowed to write data; And when the write enabling signal of the target storage block is not the first target enabling signal, determining that the current writing state of the target storage block corresponding to the storage sequence number is an unwritable state.
14. The method of claim 12, wherein the identifying whether a target number of target storage units exist in the target storage block comprises: acquiring a write enable signal of each storage unit in the target storage block; determining that the target memory cells with the target number exist in the target memory block when the second target enabling signals with the target number exist in the write enabling signals of the memory cells, wherein the second target enabling signals are enabling signals for representing that the memory cells currently allow writing data; And when the second target enabling signals of the target number are not existed in the write enabling signals of the storage units, determining that the target storage units of the target number are not existed in the target storage block.
15. The data writing system is characterized by comprising a first data distribution unit and a second data distribution unit, wherein the first data distribution unit is a special distribution unit for processing first-level cache data, and the second data distribution unit is a general distribution unit for processing non-first-level cache data; The first data distribution unit is used for receiving a first data writing request of the first-level cache unit and writing first-level cache data corresponding to the first data writing request into the on-chip storage unit; The second data distributing unit is configured to receive a second data writing request of the non-first-level cache unit, and write non-first-level cache data corresponding to the second data writing request into the on-chip storage unit.
16. A computer device, comprising: A memory and a processor, wherein the memory has stored therein a computer program which, when executed by the processor, implements the data writing method according to any of claims 1-14.
17. A computer readable storage medium, characterized in that the storage medium has stored therein a computer program which, when executed by a processor, implements the data writing method according to any of claims 1-14.

Description

Data writing method, data writing system, device and storage medium Technical Field The present disclosure relates to the field of data processing technologies, and in particular, to a data writing method, a data writing system, a device, and a storage medium. Background A Cache Memory (Cache) unit is a temporary Memory located between a processor and a Memory, and the capacity of the Cache unit is smaller than that of the Memory, but the data transmission speed of the Cache unit is far faster than that of the Memory. The first-level buffer memory (L1 buffer memory) unit is directly connected with the data bus of the processor, the data transmission speed is close to the data processing speed of the processor, and the data in the first-level buffer memory unit is called first-level buffer memory data. An On-chip Memory (On-chip Memory) unit is a high-speed Memory unit integrated inside a processor chip for storing data directly accessed by a processor. In the related art, both the first-level cache unit and the non-first-level cache unit outside the first-level cache unit need to write data into an on-chip storage unit in the processor, so that data processing is performed through the on-chip storage unit, data in the first-level cache unit is called first-level cache data, data in the non-first-level cache unit is called non-first-level cache data, the first-level cache data and the non-first-level cache data are written into the on-chip storage unit in the processor through a target data distribution unit (for example, a Demux), the target data distribution unit performs write arbitration processing on the first-level cache data and the non-first-level cache data, then write the first-level cache data and the non-first-level cache data into the on-chip storage unit according to a data write-in sequence after the write arbitration processing, a data write-in mode increases write competition of the first-level cache data, so that delay of writing the first-level cache data into the on-chip storage unit increases, write efficiency of the first-level cache data decreases, and data write-in performance of the on-chip storage unit decreases. Disclosure of Invention In order to solve the problems in the related art described above, the present disclosure provides a data writing method, a data writing system, an apparatus, and a storage medium. The first aspect of the present disclosure provides a data writing method, applied to a data writing system, where the data writing system includes a first data distribution unit and a second data distribution unit, the first data distribution unit is a dedicated distribution unit for processing first-level cache data, and the second data distribution unit is a general distribution unit for processing non-first-level cache data, and the method includes: receiving a first data writing request of a first-level cache unit through a first data distribution unit, and writing first-level cache data corresponding to the first data writing request into an on-chip storage unit through the first data distribution unit; And receiving a second data writing request of the non-primary cache unit through the second data distribution unit, and writing non-primary cache data corresponding to the second data writing request into the on-chip storage unit through the second data distribution unit. Optionally, the first data distribution unit is configured to bypass a preset arbitration processing flow, and write the first level cache data into the on-chip storage unit; The second data distribution unit is configured to write the non-primary cache data into the on-chip storage unit through the preset arbitration processing flow. Optionally, the writing, by the first data distributing unit, the first level cache data corresponding to the first data writing request into the on-chip storage unit includes: Obtaining first-level cache data through a first data distribution unit, wherein the first-level cache data comprises a plurality of target data; Sequentially storing a plurality of target data into a data buffer in a first data distribution unit according to the acquisition sequence of the plurality of target data through the first data distribution unit; And writing the plurality of target data in the data buffer into the on-chip storage unit through the first data distribution unit. Optionally, the obtaining the first level cache data through the first data distribution unit includes: Obtaining the residual buffer depth of a data buffer through a first data distribution unit; When the residual buffer depth is greater than or equal to a preset depth threshold value, acquiring first-level buffer data with the corresponding quantity of the residual buffer depth through a first data distribution unit; And when the residual buffer depth is smaller than a preset depth threshold value, controlling the first data distribution unit to stop acquiring the first-level buffer data. Optionally, the writing