CN-122018788-A - Memory control method and memory system

CN122018788ACN 122018788 ACN122018788 ACN 122018788ACN-122018788-A

Abstract

The invention discloses a memory control method and a memory system, which relate to the technical field of memory and are applied to a memory controller, and the method comprises the steps of mapping physical blocks of memory equipment into a plurality of sequential writing areas; the method comprises the steps of dynamically configuring mapping granularity for each sequential writing area according to current load, defining the number of physical blocks corresponding to a single area and a distribution mode in a storage chip by the mapping granularity, receiving a host writing request, splitting writing data into a plurality of sub data blocks according to the mapping granularity, distributing the sub data blocks to a plurality of target sequential writing areas distributed in different storage devices and different storage chips in parallel, writing the data into a corresponding physical block set by each storage device according to the mapping granularity configured by the target area, and triggering plane-level concurrent writing when the physical block set is distributed in a plurality of storage planes of the same chip. The invention obviously improves the sequential writing bandwidth of the DRAM-less SSD array through the cooperation of dynamic granularity configuration and multi-level concurrent writing.

Inventors

TANG YONGLIN
WANG WENHUA
ZHANG BIN
ZHONG LINGANG

Assignees

杭州菲数科技有限公司

Dates

Publication Date: 20260512
Application Date: 20251231

Claims (10)

1. A memory control method applied to a memory controller, the memory controller being connected to at least one memory device, the method comprising: Mapping a physical block of the storage device into a plurality of sequential write areas; configuring mapping granularity for the sequential writing area according to the current load, wherein the mapping granularity defines the number and distribution mode of physical blocks corresponding to a single sequential writing area; receiving a write request aiming at a logic address range from a host, splitting write data of the write request into a plurality of sub-data blocks, and concurrently distributing the plurality of sub-data blocks to a plurality of sequential write areas; splitting the sub data block into a plurality of data pages based on the mapping granularity of the sequential write region configuration; and writing a plurality of data pages into the physical blocks of the target sequential writing area concurrently.
2. The memory control method of claim 1, wherein the mapping granularity comprises at least one of the following configurations: The first mapping granularity is that a sequential writing area corresponds to a physical block in a storage plane; The second mapping granularity is that a sequential writing area corresponds to a logic block set formed by physical blocks in at least two different storage planes in the same storage chip; and the third mapping granularity is that one sequential writing area corresponds to a logic block set formed by physical blocks in all storage planes in the same memory chip.
3. The memory control method according to claim 2, wherein configuring the mapping granularity for the sequential writing area according to the current load comprises: when the load is continuous high-capacity data writing, configuring by adopting the second mapping granularity or the third mapping granularity; And when the load is a plurality of random small-capacity data writes, configuring by adopting the first mapping granularity.
4. The method of claim 1, wherein concurrently writing the plurality of sub-data blocks into a plurality of target sequential write regions comprises: the memory controller issues a plurality of write commands directed to different memory devices in parallel; For a single memory device, the received write commands are directed to multiple sequential write areas within the device based on different memory chips.
5. The memory control method according to claim 4, characterized in that the method comprises: And for a command of writing a single sequence writing region in the storage device, if the region is configured according to the second mapping granularity or the third mapping granularity, further splitting the writing data of the region into data pieces corresponding to the number of physical blocks in the logic block set, and writing the data pieces into each physical block in the logic block set.
6. The memory control method according to claim 1, characterized in that the method further comprises: When the memory controller writes to the initial logic address of a sequential writing area for the first time, the memory device allocates one or more idle physical blocks from the corresponding one or more memory planes according to the mapping granularity of the area, and establishes a mapping relation between the sequential writing area and the allocated physical blocks.
7. The memory control method according to claim 6, characterized in that the method comprises: In response to triggering garbage collection for a sequential writing area, migrating all valid data in the sequential writing area as a whole to a newly allocated set of physical blocks; and updating the mapping relation between the sequential writing area and the physical block, and keeping the logical address presented by the sequential writing area to the memory controller unchanged.
8. A memory controller for use with a memory array comprising a plurality of memory devices, the memory controller configured to: Mapping the physical blocks of each storage device into a plurality of sequential writing areas, and dynamically configuring mapping granularity for the sequential writing areas according to the current input/output load, wherein the mapping granularity defines the number of the physical blocks corresponding to a single sequential writing area and the distribution mode of the physical blocks among different storage planes; receiving a write request from a host; Splitting the write data of the write request into a plurality of sub-data blocks based on the dynamically configured mapping granularity; Mapping and writing the plurality of sub data blocks concurrently into a plurality of target sequential writing areas, wherein the plurality of target sequential writing areas are distributed in one or more storage devices; The memory controller issues write commands in parallel while utilizing channel level concurrency between the memory devices and chip level concurrency within a single memory device.
9. A memory device for communicative connection with the memory controller of claim 8, comprising: A flash memory medium comprising a plurality of channels, a plurality of memory chips, each memory chip comprising a plurality of memory planes, each memory plane comprising a plurality of physical blocks; A device controller configured to: Receiving a write command from the memory controller, the command indicating writing data to a target sequential write area; determining a corresponding group of physical blocks according to the mapping granularity configured by the memory controller for the target sequential writing area; Writing the data to be written into the determined physical block; when the mapping granularity indicates that the target sequential writing area corresponds to a logic block set formed by physical blocks in a plurality of storage planes in the same storage chip, the equipment controller controls the flash memory medium to write data to be written into each physical block in the logic block set in a concurrent manner so as to realize plane level concurrency.
10. A storage system, comprising: the memory controller of claim 8; and a plurality of memory devices as claimed in claim 9, connected to the memory controller by a plurality of channels; The memory controller splits a write request of a host into a plurality of sub-data blocks and controls the sub-data blocks to be written into a plurality of sequential writing areas distributed on a plurality of memory devices in parallel, so that multi-level hardware concurrent writing among channels, chips and planes in the chips is realized in the memory system at the same time.

Description

Memory control method and memory system Technical Field The application relates to the technical field of storage, in particular to a memory control method and a memory system. Background In the technical field of storage, a traditional Solid State Disk (SSD) is usually equipped with an independent Dynamic Random Access Memory (DRAM) chip for caching an address mapping table and user data, so as to improve the read-write access speed, and the existence of the external DRAM significantly increases the hardware cost, power consumption and design complexity of the SSD. DRAM-less SSD disks offer significant advantages over DRAM-bearing SSD disks in terms of cost, power consumption, etc., but in practical applications, shortcomings in performance, task processing capacity, and lifetime become particularly pronounced, especially in the context of multiple SSDs making up a large-scale storage array to provide higher capacity and reliability. Accordingly, there is a need in the art to address the performance challenges faced in large-scale array applications while maintaining the cost advantages of DRAM-less SSDs, fully mine and cooperatively utilize the parallel capabilities of the various levels of hardware from the array to the device interior through innovative control methods, maximize sequential write bandwidth and optimize data storage patterns. However, in the prior art, the storage control method is not fully adapted and effectively utilizes the inherent multi-level parallel hardware architecture (multi-channel, multi-storage chip, multi-storage plane) in the SSD, so that the actual bandwidth often cannot approach the theoretical peak value of the hardware when the storage array is written in sequence. Meanwhile, the frequent small-granularity random writing operation not only aggravates the garbage recycling pressure of the two stages of the storage array and the SSD device, but also obviously increases the writing amplification effect, thereby further influencing the overall service life of the SSD. Disclosure of Invention Various embodiments of the present specification describe a memory control method. In a first aspect, embodiments of the present disclosure provide a memory control method applied to a memory controller, where the memory controller is connected to at least one memory module, the method including: Mapping a physical block of the memory module into a plurality of sequential write areas; configuring mapping granularity for the sequential writing area according to the current load, wherein the mapping granularity defines the number and distribution mode of physical blocks corresponding to a single sequential writing area; receiving a write request aiming at a logic address range from a host, splitting write data of the write request into a plurality of sub data blocks, concurrently distributing the plurality of sub data blocks to a plurality of sequential write-in areas, and customizing the number of the sub data blocks according to requirements; splitting the sub data block into a plurality of data pages based on the mapping granularity of the sequential write region configuration; and writing a plurality of data pages into the physical blocks of the target sequential writing area concurrently. Further, the mapping granularity includes at least one of the following configurations: The first mapping granularity is that a sequential writing area corresponds to a physical block in a storage plane; The second mapping granularity is that a sequential writing area corresponds to a logic block set formed by physical blocks in at least two different storage planes in the same storage chip; and the third mapping granularity is that one sequential writing area corresponds to a logic block set formed by physical blocks in all storage planes in the same memory chip. Further, the configuring the mapping granularity for the sequential writing area according to the current load includes: when the load is continuous high-capacity data writing, configuring by adopting the second mapping granularity or the third mapping granularity; And when the load is a plurality of random small-capacity data writes, configuring by adopting the first mapping granularity. Further, concurrently writing the plurality of sub-data blocks into the plurality of target sequential write areas includes: The memory controller issues a plurality of write commands directed to different memory modules in parallel; For a single memory module, the received write commands are directed to multiple sequential write areas within the device based on different memory chips. Further, the method comprises the steps of: And for a command of writing a single sequence writing region in the memory module, if the region is configured according to the second mapping granularity or the third mapping granularity, further splitting the writing data of the region into data pieces corresponding to the number of physical blocks in the logic block set, and