CN-122018790-A - Processing system for realizing waveform file storage playback based on DDR3

CN122018790ACN 122018790 ACN122018790 ACN 122018790ACN-122018790-A

Abstract

The invention provides a processing system for realizing waveform file storage playback based on DDR 3. The system is realized based on a ZYNQ architecture, a PS end reads a waveform file from a SATA disk and moves the waveform file to a PL end DDR3 through an AXI bus, and during playback, the PL end continuously takes the data from the DDR3 according to an address pointer according to parameters such as sampling rate, power and the like issued by the PS end in real time, and drives a DA chip to output a radio frequency signal. And a 'frame header + length + data' protocol handshake is adopted between PS-PL, and the PL end manages data by using a FIFO-DDR3 secondary buffer memory to support segment circulation, speed change and zero interruption playback. The system can realize the functions of playing the waveform file with the maximum sampling rate of 800M, supporting continuous playing of different maximum file sizes under different sampling rates, controlling waveform output amplitude, playing times, playing period and the like, and has the advantages of simple realization method and strong portability, and can be applied to various FPGA chip platforms.

Inventors

PENG JIE
ZHE WEIDONG
CHEN HAO
WANG LIHAO
GUO DIWEI
SHANG LEI

Assignees

成都航天通信设备有限责任公司

Dates

Publication Date: 20260512
Application Date: 20260109

Claims (10)

1. The processing system is characterized in that a ZYNQ architecture based on an FPGA is combined with display control software to issue waveform playback files and parameters, the waveform files are read from a SATA disk and transferred to the DDR3, and when the waveform needs to be played back, waveform radio frequency signals are output based on a DA chip connected with the DDR 3; The ZYNQ architecture comprises a processing system end and a programmable logic end, wherein the processing system end and the programmable logic end are connected through an AXI bus; The processing system end is used for storing the waveform file into the SATA disk, sending the waveform file to an AXI data interface of the programmable logic end through an AXI bus after reading the SATA disk file, and sending the waveform playback parameters to an AXI parameter interface of the programmable logic end; The programmable logic end is used for analyzing AXI bus transmission data, including parameter data and waveform file data, and DDR3 chip driving read-write control and DA chip radio frequency control.
2. The processing system for realizing storage and playback of the waveform file based on DDR3 according to claim 1, wherein the processing system end and the programmable logic end perform data interaction by adopting a protocol structure of frame header bit, length bit and data bit.
3. The DDR3 based waveform file storage and playback processing system of claim 2, wherein the frame header bit is used to identify a data transfer state; when the data transmission is completed, namely after the data of the processing system end is written, filling a first identification value in a frame header bit, wherein the first identification value indicates that the programmable logic end can receive the data; And when the data receiving is completed, filling a second identification value in the frame head after the data of the programmable logic end is read, which indicates that the processing system end can perform the next data interaction.
4. The processing system for realizing waveform file storage and playback based on DDR3 according to claim 3, wherein the programmable logic terminal adopts a FIFO-DDR3 collaborative caching mechanism, and realizes data storage through a FIFO cache and a DDR3 stored secondary cache.
5. The processing system for realizing storage and playback of the waveform file based on DDR3 according to claim 1, wherein the processing system operates a Reworks system.
6. The DDR3 based processing system of claim 1, wherein the waveform playback parameters comprise a waveform playback flag parameter, a waveform sample rate parameter, a power control parameter, and a reset flag parameter.
7. The processing system for realizing storage and playback of a waveform file based on DDR3 according to claim 6, wherein the size of the waveform file that can be played back by the processing system is inversely related to the waveform sampling rate set in the waveform playback parameters.
8. The processing system for realizing storage and playback of the waveform file based on DDR3 according to claim 1, wherein the DDR3 fast read-write control is realized by adopting an MIG IP core, namely DDR3 is connected with the programmable logic terminal through an MIG controller.
9. The processing system for realizing waveform file storage and playback based on DDR3 according to claim 4, wherein the method for storing waveform file data by using the processing system comprises the following steps: when the programmable logic end detects that a frame head bit in an AXI bus data interface is filled with a first identification value, waveform data of the packet is obtained according to protocol analysis, and meanwhile, the data is written into the FIFO for caching, and a FIFO data caching completion mark is generated; When the DDR3 write control module detects the FIFO data buffer finishing mark, namely starting the DDR3 write data process, reading data from the FIFO and writing the data into the DDR3, and when the FIFO is empty, filling the frame head bit in the AXI protocol with a second identification value, and at the moment, carrying out next packet data interaction by the processing system end; Until the processing system end sends the whole waveform file to the programmable logic end for DDR3 data storage, the programmable logic end can acquire the waveform file storage address area at the moment and is used for data reading operation during waveform playback.
10. The processing system for realizing waveform file storage playback based on DDR3 according to claim 9, wherein the method for performing waveform file data playback by using the processing system comprises the following steps: When detecting that a frame head bit in an AXI bus parameter interface fills a first identification value, a programmable logic end analyzes and acquires a waveform playback parameter according to a protocol, wherein the waveform playback parameter comprises a waveform playback mark parameter, a waveform sampling rate parameter, a power control parameter and a reset mark parameter; When the DDR3 read control module detects a waveform playback mark, starting a DDR3 read data process, acquiring a DDR3 data address range of data storage, and caching the read DDR3 data into the FIFO; according to the waveform sampling rate parameter, controlling the data reading period of the FIFO, ensuring continuous output of data according to the corresponding sampling rate, and enabling effective data output when the FIFO is not empty; And according to the power control parameters, carrying out corresponding size conversion on the data output by the FIFO, and sending the changed data and the enabling to the DA control module to obtain a radio frequency waveform signal with a corresponding sampling rate and a waveform signal with a corresponding power size.

Description

Processing system for realizing waveform file storage playback based on DDR3 Technical Field The invention relates to the technical field of waveform signal processing, in particular to a processing system for realizing waveform file storage and playback based on DDR 3. Background In the occasions requiring complex electromagnetic environment simulation such as radar, communication, electronic warfare and the like, the real-time storage and playback of waveform files become the core links of system verification, outfield test and training evaluation. The traditional method relies on a laboratory-level signal source instrument, and the built-in solid-state storage and radio frequency channel have excellent performance, but a single device has the advantages of quick price of hundreds of thousands of yuan, large volume and high power consumption, only supports waveform files with fixed formats, and is difficult to deploy on-board, on-board and randomly on-board. In recent years, with the promotion of the computational power of an FPGA and the popularization of a SATA/PCIe interface, a scheme of directly realizing an NVMe protocol stack by using the FPGA and completing waveform caching through an M.2 NVMe solid-state disk appears in the industry, and an attempt is made to replace an instrument with a commercial-level device. However, the NVMe protocol is complex in command set, a large amount of bottom details such as queue management, PRP list analysis, power consumption state switching and the like are required to be completed by the FPGA at a link layer, the code quantity exceeds 2 ten thousand lines, the development period is as long as a plurality of months, meanwhile, the problems such as chain dropping, increased error rate and the like of the NVMe disc under the external field conditions such as high and low temperature, vibration, low air pressure and the like frequently occur, and the reliability design further increases the logic resource consumption and the system complexity. In addition, the pain of 'large file high-speed random playback' is not solved in both an instrument scheme and an NVMe scheme, namely when the file size exceeds the DDR capacity in an FPGA chip, a solid state disk can only be used as a streaming data source, and is read and played simultaneously, and once jump, circulation or speed change is needed in the playback process, the file needs to be re-addressed, so that millisecond interruption is caused, and the severe requirements of scenes such as coherent, frequency hopping, pulse strings and the like on continuity cannot be met. Therefore, there is a need for a new storage-playback architecture that combines cost, reliability and flexibility to implement high sample rate waveform file storage playback processing on embedded platforms. Disclosure of Invention The present invention aims to solve at least one of the above technical problems in the prior art. Therefore, the invention provides a processing system for realizing waveform file storage playback based on DDR 3. According to the processing system for realizing waveform file storage and playback based on DDR3, which is provided by the invention, a ZYNQ architecture based on an FPGA is combined with display control software to issue waveform playback files and parameters, the waveform files are read from a SATA disk and are transferred to DDR3, and when waveforms need to be played back, waveform radio frequency signals are output based on a DA chip connected with DDR 3; The ZYNQ architecture comprises a processing system end and a programmable logic end, wherein the processing system end and the programmable logic end are connected through an AXI bus; The processing system end is used for storing the waveform file into the SATA disk, sending the waveform file to an AXI data interface of the programmable logic end through an AXI bus after reading the SATA disk file, and sending the waveform playback parameters to an AXI parameter interface of the programmable logic end; The programmable logic end is used for analyzing AXI bus transmission data, including parameter data and waveform file data, and DDR3 chip driving read-write control and DA chip radio frequency control. The processing system for realizing the storage and playback of the waveform file based on DDR3 according to the technical scheme of the invention can also have the following additional technical characteristics: in the above technical solution, the processing system end and the programmable logic end use a protocol structure of frame header bit+length bit+data bit to perform data interaction. In the above technical solution, the frame header bit is used to identify a data transmission state; when the data transmission is completed, namely after the data of the processing system end is written, filling a first identification value in a frame header bit, wherein the first identification value indicates that the programmable logic end can receive the data; And