CN-122018800-A - FPGA software rapid reconstruction and loading/refreshing system

CN122018800ACN 122018800 ACN122018800 ACN 122018800ACN-122018800-A

Abstract

The invention discloses a fast reconfiguration and loading/refreshing system of FPGA software, which belongs to the technical field of satellites and mainly comprises a storage management board card, a single-machine internal interconnection and a business function board card. The storage management board mainly comprises a processor, a plurality of groups of storage particles and a control FPGA, and mainly realizes the functions of uploading, receiving, analyzing, checking, caching and fast reconstructing of software data such as the FPGA, and the plurality of groups of storage particles store the program data of the FPGA. The method and the device realize centralized storage management of a plurality of FPGA program data by adopting a shared centralized storage architecture, reduce the total storage capacity of the system and the system cost, shorten the reconstruction time of the FPGA program of the system by adopting a quick reconstruction method, provide reconstruction efficiency, realize parallel loading and refreshing of the FPGA and shorten the refreshing period, and effectively improve the single event upset resistance capability of the FPGA program in the running process and increase the stability of the on-track running function of the FPGA.

Inventors

HUANG XIAOLIANG
LI XIAONAN
WANG HUI
JIN XIAODONG
WANG WEI
Zhang Shiceng
FENG SHIXIONG
ZHANG QIANG
PANG ZONGQIANG
SUN YANHONG
WANG LIMIN
LIU SHUO
YANG CHUNYU
LIN YUANCHAO
XI SHANGBIN
Luan Shaojian

Assignees

中国电子科技集团公司第五十四研究所

Dates

Publication Date: 20260512
Application Date: 20260128

Claims (5)

1. The FPGA software rapid reconstruction and loading/refreshing system is characterized by mainly comprising a storage management board card (1) and a service function board card (3), wherein the main body of the service function board card (3) is a service FPGA; The storage management board card (1) comprises a processor, a storage particle group and a control FPGA, wherein the processor is used for receiving, analyzing, checking and caching the data of the service FPGA after uploading, realizing the storage access of the storage particles through the control FPGA, and carrying out the parallel reconstruction of the service FPGA to realize the on-orbit update of the program data; the processor sends the data to be reconstructed to the control FPGA, and when the same software program is required to be reconstructed in parallel, the control FPGA simultaneously distributes the data to a plurality of storage particle groups and writes the data into the storage particles; The loading and refreshing processes are as follows, the FPGA is controlled to concurrently clear the program state of the service FPGA to be loaded, the completion condition of the initialization of the service FPGA to be loaded is polled, after all the service FPGAs are initialized, the service FPGAs are distinguished according to functions, the parallel loading of the service FPGAs with the same functions is realized, after the service FPGAs are loaded, the FPGA is controlled to realize the parallel refreshing of the service FPGAs with the same functions, and the refreshing operation of the service FPGAs with different functional groups is sequentially completed.
2. The rapid reconfiguration and loading/refreshing system of FPGA software according to claim 1 is characterized in that a storage management board card (1) and a business function board card (3) are interconnected through a backboard, wherein loading/refreshing control information is interconnected through SLAVE SELECTMAP buses, loading and refreshing functions of a plurality of FPGAs are achieved, and in the storage management board card (1), a processor, a plurality of storage particle groups and the control FPGAs are all connected through BPI buses.
3. The rapid reconfiguration and loading/refreshing system of FPGA software according to claim 1, wherein the program software of the service FPGA is classified, the number of types of the service FPGA software is counted as M, the storage space for storing the particle group is divided into M spaces, and M types of software programs of the service FPGA are stored respectively.
4. The rapid reconfiguration and loading/refreshing system of FPGA software according to claim 1, wherein during the reconfiguration process, the processor receives the software data to be reconfigured, parses and checks the received software data, caches the software data into the memory, parses and interprets the location information of the service FPGA software memory to be reconfigured, receives the remote control command, determines the type of the reconfiguration mode to be adopted, When the same software program is parallelly reconstructed, the FPGA is controlled to send a storage particle group corresponding service FPGA software storage position area erasing command operation, the FPGA is controlled to aim at N groups of memories, simultaneously the N groups of memories are distributed to a plurality of storage particle group erasing commands, all the memories in the area to be reconstructed are waited to finish fixed storage space erasing operation, programming commands are simultaneously sent to N groups of memory particles through a BPI bus, data to be reconstructed are sent to a plurality of groups of memory particles according to bytes, each memory programming completion mark is successively read, whether timeout is waited, the specific positions of the memory particles are waited for after timeout is marked, word-by-word reconstruction of all the software data to be reconstructed is finished, when the software data reconstruction is finished, the N groups of memory particles are successively read, verification results are returned to the ground through a telemetry channel, and the software reconstruction flow is completed; When a plurality of software programs are reconstructed in parallel, a processor sequentially receives a plurality of pieces of software data to be reconstructed, analyzes and checks the received data, caches the received data to different position areas in a memory, analyzes and interprets a plurality of pieces of specific position information of a service FPGA software memory required to be reconstructed, receives a remote control instruction, determines a type of reconstruction mode, controls the FPGA to send an erasure command operation of the storage position area of the storage particle group corresponding to the plurality of service FPGA software, controls the FPGA to sequentially distribute the erasure command of the storage particle group to N groups of memories, waits for all the storage areas to be reconstructed to finish the fixed storage space erasure operation, sequentially sends a programming command to the N groups of memory particles through a BPI bus, sends the data to be reconstructed to a plurality of groups of storage particles according to bytes, reads each memory programming completion mark, determines whether the time-out is waited for finishing, marks the time-out wait for the specific position of the storage particle, completes the word-by-word reconstruction of all the cached data, sequentially reads the data to the N groups of memory particles when the software data reconstruction is completed, and checks the N groups of memory particles are sequentially read and returns to the ground through a telemetry channel, and completes the parallel reconstruction flow of the plurality of software.
5. The rapid FPGA software reconfiguration and loading/refreshing system of claim 1 wherein each service FPGA front end has an isolation interface circuit connected thereto.

Description

FPGA software rapid reconstruction and loading/refreshing system Technical Field The invention relates to a rapid reconstruction and loading/refreshing system of FPGA software, belongs to the technical field of satellites, and is particularly suitable for a complex satellite loading device containing a plurality of FPGAs in products. Background With the increasing complexity of satellite load functions, the product integration level is higher and higher, tens of FPGAs or even hundreds of FPGAs are integrated in the satellite load, and a plurality of FPGAs work cooperatively in a complex electronic system. The traditional multi-chip FPGA software storage management, reconstruction and loading scheme has some defects: The storage resources are seriously redundant, each FPGA is independently provided with at least two memories of a curing memory and a filling memory, the FPGA with the same function needs to repeatedly store programs, the occupation amount of the storage resources is linearly increased along with the number of the FPGA, the hardware cost is wasted, the number of the memories on the load is large, the price of the load product is high, and the development trend of the low-cost load product is not met; The reconstruction transmission efficiency is low, namely external reconstruction data is transmitted to the local storage through a link, a parallel scheduling mechanism is lacked, and the requirement of fast update of batch FPGA programs cannot be met; The starting time is long, a plurality of FPGAs adopt a 'piece-by-piece loading' mode, the total starting time is N times of the loading time of a single piece (N is the number of FPGAs), and the quick starting requirement of the system after the on-orbit startup of the load of the low-orbit satellite of the Internet can not be met. After the starting, the FPGA needs to be refreshed, the accumulated influence of single event upset during the operation of the FPGA is eliminated, the refreshing mode of 'piece-by-piece refreshing' is adopted at present, and the total refreshing period of the FPGA is long. In the prior art, although the multi-chip FPGA realizes the centralized storage and the fractional FPGA loading and refreshing technology, the integrated coordination of centralized storage sharing-parallel reconstruction transmission-multi-FPGA parallel loading/refreshing is not realized, and the problems of multi-chip FPGA software storage management, rapid reconstruction and rapid loading and refreshing schemes cannot be thoroughly solved. Disclosure of Invention Aiming at the problems in the background art, the invention provides a centralized storage management architecture of FPGA software, which can realize rapid reconstruction of a plurality of FPGA program data and parallel loading/refreshing of a plurality of FPGAs. The method solves the problems of large storage space requirement capacity and storage resource redundancy of a plurality of FPGA (field programmable gate array) on a plurality of boards in a complex satellite processing load by adopting a centralized storage management scheme, realizes a parallel and rapid read-write method of a plurality of groups of storage particles by adopting a multi-bus access memory mode, solves the problem of rapid reconfiguration of satellite product software, aims at the problem of long loading time of the FPGA when a system is started, and aims at the FPGA with the same function, and by adopting a parallel loading and refreshing method, the system starting time is shortened and the integral refreshing period of the system is shortened. The technical method of the invention is realized as follows: The fast reconfiguration and loading/refreshing system of FPGA software mainly comprises a memory management board card and a service function board card, wherein the main body of the service function board card is a service FPGA; The storage management board card comprises a processor, a storage particle group and a control FPGA, wherein the processor is used for receiving, analyzing, checking and caching the data of the service FPGA after uploading, realizing the storage access of the storage particles through the control FPGA, and carrying out the parallel reconstruction of the service FPGA to realize the on-orbit update of the program data; the processor sends the data to be reconstructed to the control FPGA, and when the same software program is required to be reconstructed in parallel, the control FPGA simultaneously distributes the data to a plurality of storage particle groups and writes the data into the storage particles; The loading and refreshing processes are as follows, the FPGA is controlled to concurrently clear the program state of the service FPGA to be loaded, the completion condition of the initialization of the service FPGA to be loaded is polled, after all the service FPGAs are initialized, the service FPGAs are distinguished according to functions, the parallel loading of the service F