CN-122018810-A - Three-dimensional stacked memory based on memory and calculation integration and distributed interface

CN122018810ACN 122018810 ACN122018810 ACN 122018810ACN-122018810-A

Abstract

The application relates to a three-dimensional stacked memory based on a memory and a distributed interface, which comprises a computing chip, a memory chip, a three-dimensional integrated high-speed channel and a data interaction sampling mechanism, wherein the computing chip is used for executing a computing task, the memory chip comprises a plurality of independently addressed memory spaces, the three-dimensional integrated high-speed channel is integrated with the computing chip by adopting a three-dimensional stacked packaging technology and comprises a plurality of independent distributed interfaces, the computing chip accesses the plurality of independently addressed memory spaces in parallel through the plurality of independent distributed interfaces, and the data interaction sampling mechanism of the computing chip and the memory chip comprises at least one of asynchronous data interaction based on delay time sequence information, asynchronous data interaction based on data effective signals and synchronous data interaction based on clocks, and can flexibly select the most suitable communication mode according to the requirements of an application scene on time sequence allowance, power consumption budget and design complexity or adopt a composite scheme to optimize the energy efficiency under the communication scene of the distributed interfaces.

Inventors

CHEN PEIYU
YE LE
WANG ZHIXUAN
LIU YING

Assignees

无锡微纳核芯电子科技有限公司
杭州微纳核芯电子科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260203

Claims (11)

1. A memory-integrated and distributed interface-based three-dimensional stacked memory comprising: The computing chip is used for executing computing tasks; The memory chip and the computing chip are integrated by adopting a three-dimensional stacking packaging technology and form a three-dimensional integrated high-speed channel, and the three-dimensional integrated high-speed channel comprises a plurality of independent distributed interfaces; The computing chip accesses the plurality of independently addressed storage spaces in parallel through the plurality of independent distributed interfaces, and the data interaction sampling mechanism of the computing chip and the storage chip comprises at least one of the following: Asynchronous data interaction based on delay time sequence information, asynchronous data interaction based on a data valid signal, and synchronous data interaction based on a clock.
2. The memory integrated and distributed interface based three-dimensional stacked memory of claim 1, wherein the compute chip and the memory chip data interaction sampling comprises a read operation and a write operation, the read operation being the same as or different from a data interaction sampling mechanism of the write operation.
3. The memory and distributed interface based three-dimensional stacked memory of claim 2, wherein the asynchronous data interaction based on latency timing information comprises: in the writing operation, the computing chip sends data in sequence according to the time sequence requirement of the memory chip, and does not transmit a writing clock signal and a writing data valid signal; In the read operation, the computing chip samples the read data according to a fixed delay timing requirement and is independent of a read clock signal and a read data valid signal.
4. The integrated and distributed interface based three-dimensional stacked memory of claim 2, wherein the asynchronous data interaction based on data valid signals comprises: In the writing operation, the computing chip synchronously sends a writing data valid signal to the memory chip, and the memory chip responds to the valid level of the signal to sample data; in the read operation, the memory chip feeds back a read data valid signal synchronized with read data to the computing chip, and the computing chip performs data sampling in response to the valid level of the signal.
5. The integrated and distributed interface based three-dimensional stacked memory of claim 2, wherein the clock signal based synchronous data interaction comprises: In both the write operation and the read operation, the transmission and reception of data are synchronized with the edges of the clock signal; the clock signal sources comprise a new clock generated by the memory chip, a clock which is fed back by the memory chip and is homologous to the computing chip, or a synchronous clock forwarded by the memory chip.
6. The integrated and distributed interface based three-dimensional stacked memory of any one of claims 1-5, wherein critical interface signals of the plurality of independent distributed interfaces comprise one or more of: activation, precharge and request signals for the read operation and the write operation, respectively; Address signals including the memory space, row and column information for the memory space; a data signal including data content and ECC check information; timing control, data valid, or clock signals matched to the selected data communication mode.
7. The memory integrated and distributed interface based three-dimensional stacked memory of claim 6, wherein the read address signals and the write address signals share the same set of physical transmission lines, and wherein a single address signal includes at least two of a memory space address, a row address of a memory space, and column address information in a coded or time division multiplexed manner.
8. The integrated and distributed interface based three-dimensional stacked memory of claim 6, The read control interface and the write control interface are configured to share the same group of signal lines or two groups of independent signal lines; the read data interface and the write data interface are configured as two unidirectional transmission interfaces or share one bidirectional transmission port.
9. The integrated and distributed interface based three-dimensional stacked memory of claim 7, wherein the critical interface signals further comprise auxiliary function signals comprising at least one of: A refresh signal for maintaining the data retention characteristic; register read-write signals for configuring interface parameters; and interrupt signals for system reset and exception handling.
10. The integrated and distributed interface based three-dimensional stacked memory of any one of claims 1-5, further comprising interface means disposed on the memory chip or the computing chip for data interaction with an external host device.
11. The integrated and distributed interface based three-dimensional stacked memory of any of claims 1-5, wherein the three-dimensional stacked packaging technique comprises at least one of hybrid bonding, through silicon vias, flip chip, and micro bump connections.

Description

Three-dimensional stacked memory based on memory and calculation integration and distributed interface Technical Field The application relates to the field of chips, in particular to a three-dimensional stacked memory based on a memory and a distributed interface. Background The memory is typically made up of a plurality of memory spaces and data interaction is accomplished through peripheral interface circuitry. Traditional memories (e.g. DDR series) rely mainly on peripheral interface protocols defined by international standards (e.g. JEDEC) for sequential access to internal memory space by an external controller by command addressing (specifying memory space, row, column addresses). With the development of semiconductor technology, three-dimensional stacked memories have been developed. The architecture integrates the computing chip and the storage chip in the vertical direction by utilizing an advanced packaging technology, and can realize parallel and distributed direct access of the computing chip to a plurality of internal storage spaces, thereby remarkably improving the data transmission bandwidth and relieving the problem of a storage wall. However, existing international or national standard protocols are mainly directed to peripheral interface circuits of conventional memories, and are not formulated for the storage space interconnect interface within the three-dimensional stacked memory. If the original interface inside the traditional memory is directly used, the memory efficiency is low due to the lack of optimization for the distributed memory access characteristics (such as high concurrency and short paths), and the performance advantage of the three-dimensional stacked architecture cannot be fully exerted. Thus, there is a need for a memory space interface protocol that is specific to three-dimensional stacked memory. Disclosure of Invention In view of the above problems, an embodiment of the present application provides a three-dimensional stacked memory based on a memory and a distributed interface, including: The computing chip is used for executing computing tasks; The memory chip comprises a plurality of independently addressed memory spaces, is integrated with the computing chip by adopting a three-dimensional stacking packaging technology and forms a three-dimensional integrated high-speed channel, and the three-dimensional integrated high-speed channel comprises a plurality of independent distributed interfaces; The computing chip accesses the plurality of independently addressed storage spaces in parallel through the plurality of independent distributed interfaces, and the data interaction sampling mechanism of the computing chip and the storage chip comprises at least one of the following: Asynchronous data interaction based on delay time sequence information, asynchronous data interaction based on a data valid signal, and synchronous data interaction based on a clock. The application improves the access parallelism and the overall bandwidth of the system through the three-dimensional stacking and the distributed access architecture, and the data interaction sampling mechanism has flexibility and adaptability and can be flexibly switched between different mechanisms based on application scenes. Optionally, the data interaction sampling of the computing chip and the memory chip includes a read operation and a write operation, and the read operation and the data interaction sampling mechanism of the write operation are the same or different. Optionally, the asynchronous data interaction based on the delay time sequence information comprises that in a write operation, the computing chip sequentially transmits data according to the time sequence requirement of the memory chip and does not transmit a write clock signal and a write data valid signal, and in a read operation, the computing chip samples read data according to the fixed delay time sequence requirement and does not depend on the read clock signal and the read data valid signal. By the design, the overturning power consumption of clock signals and handshake signals is eliminated, the occupation of TSV (through silicon via) connecting lines is reduced in a three-dimensional stacked distributed application scene, and lower interconnection overhead is realized on the premise of controllable time sequence. Optionally, the asynchronous data interaction based on the data valid signal comprises that in a writing operation, the computing chip synchronously sends a write data valid signal to the memory chip, the memory chip conducts data sampling in response to the valid level of the signal, and in a reading operation, the memory chip feeds back a read data valid signal synchronous with read data to the computing chip, and the computing chip conducts data sampling in response to the valid level of the signal. By the design, data synchronization is realized through handshake signals (effective signals), dependence on a global clock tr