CN-122018821-A - Processor, data processing method, chip, display card and electronic equipment

Abstract

The disclosure provides a processor, a data processing method, a chip, a display card and electronic equipment, and relates to the technical field of integrated circuits. The processor comprises an operation unit and a memory access, wherein the operation unit is used for sending a data read-write request to the memory access, the data read-write request comprises data type conversion information, and the memory access is used for carrying out data type conversion on original data according to the data type conversion information under the condition that the data type conversion of the original data is required according to the data type conversion information, so as to obtain target data. The processor can perform corresponding data conversion processing on the access path, and can reduce the extra operation of the processor.

Inventors

• Request for anonymity
• Request for anonymity

Assignees

• 摩尔线程智能科技(北京)股份有限公司

Dates

Publication Date

20260512

Application Date

20260410

Claims (17)

1. 1. A processor is characterized in that the processor comprises an operation unit and a memory access path, wherein, The operation unit is used for sending a data read-write request to the access path, wherein the data read-write request comprises data type conversion information; The access path is configured to perform data type conversion on the original data according to the data type conversion information under the condition that it is determined that the data type conversion is required on the original data according to the data type conversion information, so as to obtain target data.
2. 2. The processor according to claim 1, wherein the access path comprises a multi-level cache for transmitting the original data and/or the target data, and wherein a data conversion unit is provided in at least one of the multi-level caches, The data conversion unit is used for carrying out data type conversion on the original data according to the data type conversion information to obtain the target data.
3. 3. The processor of claim 2, wherein the processor further comprises a processor controller, The operation unit is used for sending a data read-write request aiming at a target memory to the access path, wherein the multi-level cache comprises a first cache and a second cache, the first cache is connected with the operation unit, and the second cache is connected with the target memory; The data conversion unit of the target cache is used for carrying out data type conversion on the original data to obtain the target data, wherein the target cache is the first cache or the second cache, the target cache is determined based on the type of the data read-write request and/or the data type conversion information, and the type of the data read-write request comprises a data read request and a data write request.
4. 4. A processor according to claim 3, wherein the data type conversion information comprises an original data type and a target data type; The access path is further configured to determine that data type conversion is required for the original data if the original data type and the target data type are different.
5. 5. The processor of claim 3, wherein the first cache and the second cache are different levels of cache or the same level of cache in the multi-level cache.
6. 6. The processor of claim 4, wherein the first cache is the target cache if the type of data read-write request is a data write request and the bit width of the target data type is less than the bit width of the original data type.
7. 7. The processor of claim 4, wherein the second cache is the target cache if the type of data read-write request is a data write request and the bit width of the target data type is greater than the bit width of the original data type.
8. 8. A processor according to claim 3, wherein the type of data read-write request is a data write request, the data read-write request further comprising a target data address; the access path is used for writing the target data into the target memory according to the target data address.
9. 9. The processor of claim 4, wherein the second cache is the target cache if the type of data read-write request is a data read request and the bit width of the target data type is less than the bit width of the original data type.
10. 10. The processor of claim 4, wherein the first cache is the target cache if the type of data read-write request is a data read request and the bit width of the target data type is greater than the bit width of the original data type.
11. 11. A processor according to claim 3, wherein the type of data read-write request is a data read request, the data read-write request further comprising an original data address and a requested data length; the access path is further configured to read the original data from the target memory according to the original data address and the request data length.
12. 12. The processor of claim 4, further comprising a main memory, wherein the target memory is the main memory, the first cache is a first level cache, the second cache is a last level cache, and a data conversion unit is disposed in the first level cache, The first level cache is configured to determine, when the data read-write request is a data write request, the original data based on the data read-write request; A data conversion unit in the first level cache, configured to convert the original data into the target data when the bit width of the target data type is smaller than the bit width of the original data type; the first-level cache is further configured to send the target data to the last-level cache; And the final stage cache is used for writing the target data into the main memory.
13. 13. The processor of claim 12, wherein a data conversion unit is disposed within the last level cache, wherein, The second-stage cache is configured to read the original data from the main memory according to the data read request when the data read-write request is a data read request; a data conversion unit in the final stage buffer, configured to convert the original data into the target data when the bit width of the target data type is smaller than the bit width of the original data type; The second-level cache is further configured to send the target data to the first-level cache.
14. 14. A data processing method, applied to a processor, the processor including an arithmetic unit and a memory access, the method comprising: The operation unit sends a data read-write request to the access path, wherein the data read-write request comprises data type conversion information; And under the condition that the access path determines that the data type conversion needs to be carried out on the original data according to the data type conversion information, carrying out the data type conversion on the original data based on the data type conversion information to obtain target data.
15. 15. A chip comprising the processor of any one of claims 1-13.
16. 16. A graphics card comprising the chip of claim 15.
17. 17. An electronic device, comprising: at least one processor, and A memory communicatively coupled to the at least one processor, wherein, The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the data processing method of claim 14.

Description

Processor, data processing method, chip, display card and electronic equipment Technical Field The disclosure relates to the technical field of integrated circuits, and in particular relates to a processor, a data processing method, a chip, a display card and electronic equipment. Background For a hardware processor, data access is performed through a data path. Since the bandwidth that the data path can provide is fixed, the smaller the amount of data accessed, the smaller the amount of occupation of the hardware access path, and correspondingly the more requests that can be accessed in parallel. Disclosure of Invention The embodiment of the disclosure provides a processor, a data processing method, a chip, a display card and electronic equipment. In a first aspect, an embodiment of the present disclosure provides a processor, where the processor includes an operation unit and a memory access, where the operation unit is configured to send a data read-write request to the memory access, where the data read-write request includes data type conversion information, and the memory access is configured to perform data type conversion on original data according to the data type conversion information when it is determined that the data type conversion is required on the original data according to the data type conversion information, so as to obtain target data. In a second aspect, the embodiment of the disclosure further provides a data processing method, which is applied to a processor, wherein the processor comprises an operation unit and a memory access, the method comprises the steps that the operation unit sends a data read-write request to the memory access, the data read-write request comprises data type conversion information, and the memory access performs data type conversion on original data according to the data type conversion information under the condition that the memory access determines that the original data needs to be subjected to data type conversion according to the data type conversion information, so that target data is obtained. In a third aspect, embodiments of the present disclosure provide a chip including the processor in the first aspect. In a fourth aspect, an embodiment of the present disclosure provides a graphics card, including the chip in the fourth aspect. In a fifth aspect, an embodiment of the present disclosure provides an electronic device comprising at least one processor, and a memory communicatively coupled to the at least one processor, wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the data processing method as described in the second aspect. In the processor provided by the embodiment of the disclosure, since the data read-write request sent to the access path by the operation unit includes data type conversion information, the access path can convert the original data into the target data according to the data type conversion information, and then read or write the target data into the corresponding address. Compared with the related art, the processor disclosed by the invention does not need to use extra special instructions to perform data type conversion on the original data, and improves the data reading and writing efficiency. In addition, the processor provided by the disclosure can perform data type conversion on the original data in the access path inside the processor, and can further improve the data reading and writing efficiency. Drawings Other features, objects and advantages of the present disclosure will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings: FIG. 1a is a block diagram of a processor provided in an embodiment of the present disclosure; FIG. 1b is a block diagram of yet another processor provided by an embodiment of the present disclosure; FIG. 2 is a block diagram of a memory access according to an embodiment of the present disclosure; FIG. 3 is a schematic diagram of a structure of a memory access according to an embodiment of the disclosure; FIG. 4 is a block diagram of yet another processor provided by an embodiment of the present disclosure; FIG. 5 is a schematic diagram of a processor according to an embodiment of the present disclosure in connection with a specific scenario; FIG. 6 is a flowchart of a data processing method according to an embodiment of the present disclosure; fig. 7 is a schematic hardware structure of an electronic device according to an embodiment of the disclosure. Detailed Description Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications o