CN-122018849-A - FPGA-based distributed acoustic sensing signal processing method, system, medium and product

CN122018849ACN 122018849 ACN122018849 ACN 122018849ACN-122018849-A

Abstract

A distributed acoustic sensing signal processing method, system, medium and product based on FPGA relate to the field of signal processing. The method comprises the steps of generating corresponding data effective signals and frame end signals based on pulse repetition periods of distributed acoustic sensing signals, partitioning preset-order complex coefficients of a plurality of frequency bands into heterogeneous memories on an FPGA (field programmable gate array), time-sharing scheduling finite-length unit impulse response filter operations of the frequency bands to a same group of complex multiplication operation units, performing complex multiplication operations on input signals to obtain a plurality of product accumulation results, performing multistage hierarchical parallel accumulation on the plurality of product accumulation results, performing delay processing on the data effective signals and the frame end signals through a delay compensation mechanism, generating control signals aligned with output time sequences of the final filter results, and controlling final output based on the pulse repetition periods and the control signals. By implementing the technical scheme, efficient filtering processing of the multi-band signals can be realized.

Inventors

FU HAN
TANG ZEKUN
ZHANG YONGHUA
CHEN YUNSHEN
HU YU
Ke Xianrong
LIAO YAQI

Assignees

北京中拓新源科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260413

Claims (10)

1. The distributed acoustic sensing signal processing method based on the FPGA is characterized by comprising the following steps of: Acquiring a distributed acoustic sensing signal to be processed, and generating a corresponding data effective signal and an end-of-frame signal based on a pulse repetition period of the distributed acoustic sensing signal; Partitioning preset-order complex coefficients of a plurality of frequency bands into heterogeneous memories on an FPGA chip based on frequency band priorities, wherein the priorities are determined based on signal energy duty ratios of the frequency bands, the preset-order complex coefficients of a first frequency band with the highest signal energy duty ratio are stored in a first type memory, the preset-order complex coefficients of a second frequency band except the first frequency band are stored in a second type memory, and the access speed of the first type memory is higher than that of the second type memory; Determining a system processing time sequence based on the pulse repetition period, and according to the time sequence and storage positions configured by the preset-order complex coefficient partition, performing time-sharing scheduling on finite-length unit impulse response filtering operation of the plurality of frequency bands to a same group of complex multiplication operation units, so that in an operation time window corresponding to a target frequency band, the preset-order complex coefficient is read from a corresponding first-class memory or second-class memory according to the storage position of the target frequency band, and is input to the complex multiplication operation units, wherein the target frequency band is any one of the plurality of frequency bands; in the operation time window, complex multiplication operation is carried out on an input signal by utilizing a preset-order complex coefficient input to the complex multiplication operation unit to obtain a plurality of product accumulation results, multi-stage hierarchical parallel accumulation is carried out on the product accumulation results, each stage of accumulation carries out pairwise summation on the results output by the previous stage to compress the number of nodes until a final filtering result of the target frequency band is obtained; And carrying out delay processing on the data valid signal and the frame end signal through a delay compensation mechanism, generating a control signal aligned with the output time sequence of the final filtering result, and controlling final output based on the pulse repetition period and the control signal.
2. The FPGA-based distributed acoustic sensor signal processing method of claim 1, wherein the determining a system processing timing based on the pulse repetition period comprises: Determining the time length of a single pulse repetition period and the corresponding total sampling point number based on the system sampling rate and the pulse repetition period; Dividing the time length according to preset operation weights of the frequency bands, distributing a continuous time segment for each frequency band, wherein all the time segments are connected end to end and the sum is equal to the pulse repetition period; Establishing a mapping relation between the system clock count and the frequency band operation, so that when the system clock count falls into a time segment allocated by a third frequency band, the filtering operation of the third frequency band is automatically triggered, wherein the third frequency band is any one of the frequency bands; the system processing time sequence is determined based on the time slice and the mapping relation, so that the complex multiplication operation unit processes signals of one frequency band at each moment, and the frequency bands are sequentially and circularly processed.
3. The FPGA-based distributed acoustic sensor signal processing method of claim 1, wherein the plurality of multiply-accumulate results comprises a preset order number real part multiply-accumulate result and a preset order number imaginary part multiply-accumulate result, the performing multistage hierarchical parallel accumulation on the plurality of multiply-accumulate results comprising: Pairing the preset order real part product results in pairs in sequence to form a real part node pair, recording the residual single real part product result as a real part remainder, constructing a real part input node set based on the real part node pair and the real part remainder, pairing the preset order imaginary part product results in pairs in sequence to form an imaginary part node pair, recording the residual single imaginary part product result as an imaginary part remainder, and constructing an imaginary part input node set based on the imaginary part node pair and the imaginary part remainder; Performing synchronous summation on all real part node pairs in the real part input node set through a preset number of parallel adders to generate a real part compression result set, merging the real part remainder into the real part compression result set, performing synchronous summation on all imaginary part node pairs in the imaginary part node pair through the preset number of parallel adders to generate an imaginary part compression result set, and merging the imaginary part remainder into the imaginary part compression result set; taking the real part compression result set as a new real part input node set, taking the imaginary part compression result set as a new imaginary part input node set, and repeatedly executing the previous step until the real part nodes are compressed into a single real part result and the imaginary part nodes are compressed into a single imaginary part result; and respectively outputting the single real part result and the single imaginary part result as a final real part filtering result and a final imaginary part filtering result of the target frequency band.
4. The FPGA-based distributed acoustic sensor signal processing method of claim 1, wherein the delay processing is performed on the data valid signal and the end-of-frame signal by a delay compensation mechanism to generate a control signal aligned with the final filtering result output timing, specifically comprising: Respectively constructing a data validity delay chain and a frame end signal delay chain according to the total delay stages of the multistage hierarchical parallel accumulation, wherein the data validity delay chain and the frame end signal delay chain both comprise a plurality of cascaded triggers of the total delay stages; The data effective signal is input into the data effective delay chain and is transmitted step by the total delay progression for a plurality of clock cycles, a regenerated synchronous data effective signal is generated, and the frame end signal is input into the frame end signal delay chain and is transmitted step by the total delay progression for a plurality of clock cycles, and a regenerated synchronous frame end signal is generated; Continuously sampling real part and imaginary part data of the final filtering result in an effective period when the effective signal of the regenerated synchronous data is at a high level to obtain sampling data, and checking whether the phase alignment accuracy of the effective signal of the regenerated synchronous data and the final filtering result meets the requirement or not by checking the phase continuity of the sampling data in the effective period; and when the phase alignment precision meets the requirement, the effective signal of the regeneration synchronous data and the end signal of the regeneration synchronous frame are used as control signals and are synchronously output with the final filtering result.
5. The FPGA-based distributed acoustic sensor signal processing method according to claim 4, wherein the verifying the phase continuity of the sampled data in the effective period to verify whether the phase alignment accuracy of the regenerated synchronous data effective signal and the final filtering result meets the requirement specifically comprises: selecting a target adder with the largest delay in the multistage hierarchical parallel accumulation as a monitoring point, and monitoring the stable establishment time allowance between the effective data and the sampling of a register of the next stage of output signals of the target adder in real time; When the stable establishment time allowance is lower than a dynamic safety threshold, calculating a delay clock cycle number needing additional compensation as a delay compensation increment according to the difference value between the stable establishment time allowance and the dynamic safety threshold and the system clock cycle; According to the delay compensation increment, by-pass or access a trigger of a preset level is realized by controlling a data selector arranged at the input end of each level of trigger in the data validity delay chain and the end-of-frame signal delay chain so as to adjust the valid depth of the data validity delay chain and the end-of-frame signal delay chain; and after the effective depth is adjusted, recovering the check phase continuity.
6. The FPGA-based distributed acoustic sensor signal processing method of claim 1, wherein the partitioning of the preset-order complex coefficients of the plurality of frequency bands into the FPGA-chip heterogeneous memory based on the frequency band priorities comprises: The method comprises the steps of carrying out weighted summation on a signal energy history mean value of each frequency band, a signal mutation frequency in a preset history period and a preset system level importance weight through a preset weighted scoring function to generate a comprehensive priority score; The method comprises the steps of performing descending order sequencing on all frequency bands according to the comprehensive priority score, calculating the upper limit of the number of frequency bands which can be accommodated by a first type of memory according to the ratio of the total capacity of the first type of memory to the data volume of single frequency band complex coefficients, defining a first frequency band according to the upper limit of the number of frequency bands, preloading preset-order complex coefficients of the first frequency band to the first type of memory, and storing preset-order complex coefficients of the residual frequency band in the second type of memory; The first frequency bands in the first type of memories are secondarily ordered according to the comprehensive priority scores, and the first frequency bands are sequentially stored in the memory blocks with increasing access delay according to the comprehensive priority scores from high to low; And generating a mapping table of the frequency band ID-memory type-memory block address, programming the mapping table into a configuration memory of the FPGA, and loading complex coefficients of preset orders of each frequency band from external storage to corresponding heterogeneous memory partitions on the FPGA chip according to the mapping table when the system is electrified and initialized.
7. The FPGA-based distributed acoustic sensor signal processing method of claim 2, wherein the controlling the final output based on the pulse repetition period and the control signal comprises: Calculating the number of filtering results to be cached in the current pulse repetition period of each frequency band in real time according to the time segments allocated to each frequency band, and allocating independent annular cache areas for each frequency band according to the number of filtering results; configuring independent write pointers and read pointers for each annular buffer area, and managing the write pointers and the read pointers in a cyclic incremental mode; in the operation time window corresponding to each frequency band, using a time-sharing write-enabling signal generated by the operation time window as write trigger to control the increment of a write pointer of a corresponding annular buffer zone, and writing the filtering result of the current frequency band into a storage address pointed by the write pointer; Generating a global read enable pulse with the end of frame signal at the end of each pulse repetition period; responding to the global reading enabling pulse, simultaneously resetting the reading pointers of all the annular cache areas to the initial address, starting a synchronous reading process, and sequentially reading all the cache data from each annular cache area; And splicing and assembling real part data and imaginary part data of all frequency bands read out at the same moment into a multiband output data frame according to a preset sequence, generating a frame effective identification signal synchronous with the transmission process of the multiband output data frame, and determining the final output to an external system by using a high-level effective window of the frame effective identification signal.
8. A computer system comprising a memory, a processor and a computer program stored on the memory, characterized in that the processor executes the computer program to carry out the steps of the method according to any one of claims 1-7.
9. A computer readable storage medium having stored thereon a computer program/instruction, which when executed by a processor, implements the steps of the method of any of claims 1-7.
10. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method of any of claims 1-7.

Description

FPGA-based distributed acoustic sensing signal processing method, system, medium and product Technical Field The application relates to the field of signal processing, in particular to a distributed acoustic sensing signal processing method, system, medium and product based on FPGA. Background With the rapid development of information technology, the distributed acoustic sensing technology has great application potential in a plurality of fields. The system can monitor and analyze acoustic signals in a large-scale space in real time, and plays an important role in the fields of petroleum and natural gas exploration, perimeter security protection, structural health monitoring and the like. The distributed acoustic sensing signal processing technology is used as a core link, and the performance and the application effect of the whole system are directly affected. The high-efficiency accurate signal processing method can extract valuable information from complex acoustic signals and provide reliable basis for decisions in various fields. In the prior art, for the processing of distributed acoustic sensor signals, a conventional centralized processing architecture is generally employed. Such an architecture concentrates all signal processing tasks in one processing unit, and when processing signals of a plurality of frequency bands, it is often necessary to allocate processing resources individually for each frequency band, and to uniformly store and process coefficients of all frequency bands. The existing distributed acoustic sensing signal processing method has obvious defects, and the centralized processing architecture causes excessive burden of a processing unit, so that the requirement of large-scale signal processing cannot be met. The mode of unified storage and processing of frequency band coefficients cannot fully utilize the characteristics of different types of memories, so that the waste of storage resources is caused. Meanwhile, due to the lack of an effective processing time sequence scheduling mechanism, the real-time performance and accuracy of signal processing are difficult to ensure, and the requirements of high-efficiency and accurate signal processing in practical application cannot be met. Disclosure of Invention The application provides a distributed acoustic sensing signal processing method, a distributed acoustic sensing signal processing system, a distributed acoustic sensing signal processing medium and a distributed acoustic sensing signal processing product based on an FPGA (field programmable gate array), which effectively utilize FPGA resources, improve processing efficiency, realize efficient filtering processing of multiband signals and ensure time sequence alignment of output signals. In a first aspect, the present application provides a distributed acoustic sensing signal processing method based on an FPGA, the method comprising: Acquiring a distributed acoustic sensing signal to be processed, and generating a corresponding data effective signal and an end-of-frame signal based on a pulse repetition period of the distributed acoustic sensing signal; Partitioning preset-order complex coefficients of a plurality of frequency bands into heterogeneous memories on an FPGA chip based on frequency band priorities, wherein the priorities are determined based on signal energy duty ratios of the frequency bands, the preset-order complex coefficients of a first frequency band with the highest signal energy duty ratio are stored in a first type memory, the preset-order complex coefficients of a second frequency band except the first frequency band are stored in a second type memory, and the access speed of the first type memory is higher than that of the second type memory; Determining a system processing time sequence based on the pulse repetition period, and according to the time sequence and storage positions configured by the preset-order complex coefficient partition, performing time-sharing scheduling on finite-length unit impulse response filtering operation of the plurality of frequency bands to a same group of complex multiplication operation units, so that in an operation time window corresponding to a target frequency band, the preset-order complex coefficient is read from a corresponding first-class memory or second-class memory according to the storage position of the target frequency band, and is input to the complex multiplication operation units, wherein the target frequency band is any one of the plurality of frequency bands; in the operation time window, complex multiplication operation is carried out on an input signal by utilizing a preset-order complex coefficient input to the complex multiplication operation unit to obtain a plurality of product accumulation results, multi-stage hierarchical parallel accumulation is carried out on the product accumulation results, each stage of accumulation carries out pairwise summation on the results output by the previous stage