CN-122018854-A - Test pattern generation unit and test pattern generation device

CN122018854ACN 122018854 ACN122018854 ACN 122018854ACN-122018854-A

Abstract

The application relates to a test pattern generating unit and a test pattern generating device, wherein an address generating module respectively carries out logic operation on address data issued by a sequence controller by combining immediate data to obtain first intermediate data, the first intermediate data is combined with second register data issued by the sequence controller to serve as a data source to carry out M-path logic operation to output an address after M-path operation, a data generating module respectively carries out logic operation on fourth register data issued by the sequence controller by combining immediate data to obtain fourth intermediate data of M-path, and the fourth intermediate data of M-path and fifth register data issued by the sequence controller serve as data sources to carry out M-path logic operation to output data after M-path operation. The signal mapping module synchronously receives the M-path operated address and the M-path operated data, and outputs the physical mapped address and the data. The data sources of the address generation module and the data generation module are expanded so as to increase the diversity of test patterns and adapt to different test requirements.

Inventors

ZHANG SHUANGYANG
CHEN JUN
REN WENJUN
HOU QIONG
WEI SHILONG
XU JIAN
Ai Xueqian

Assignees

长迈半导体(成都)有限公司

Dates

Publication Date: 20260512
Application Date: 20251219

Claims (11)

1. The test pattern generating unit is characterized by comprising a sequence controller, an address generating module, a data generating module and a signal mapping module, wherein the signal mapping module is used for synchronously receiving M paths of addresses after operation and M paths of data after operation, outputting the addresses after physical mapping and the data, and M is more than or equal to 1; The address generation module respectively carries out logic operation on address data issued by the sequence controller by combining immediate data to obtain first intermediate data, the first intermediate data carries out M paths of logic operation by combining second register data issued by the sequence controller as a data source to output M paths of post-operation addresses, each path of post-operation address comprises a front edge post-operation address and a back edge post-operation address, the data generation module respectively carries out logic operation on fourth register data issued by the sequence controller by combining immediate data to obtain M paths of fourth intermediate data, the M paths of fourth intermediate data and the fifth register data issued by the sequence controller are used as data sources to carry out M paths of logic operation, and each path of post-operation data comprises front edge post-operation data and back edge post-operation data.
2. The test pattern generating unit according to claim 1, wherein the address data includes X sets of address data, Y sets of address data, and Z sets of register data, the address data is logically operated in combination with an immediate respectively to obtain first intermediate data, the first intermediate data includes X sets of first intermediate data, Y sets of first intermediate data, and Z sets of first intermediate data, the second register data are used as data sources to perform M-way logical operations, wherein each of the logical operations includes three-level logical operations.
3. The test pattern generating unit according to claim 2, wherein each path of logic operation includes three stages of logic operations, including: The first intermediate data of the X groups, the first intermediate data of the Y groups and the first intermediate data of the Z groups are used as data sources to carry out first-stage logic operation, so as to obtain second intermediate data; the second intermediate data and the Z groups of first intermediate data are used as data sources to carry out second-stage logic operation, and third intermediate data are obtained; And performing third-stage logic operation by taking the third intermediate data and the second register data as data sources to obtain a front edge operated address and a rear edge operated address.
4. A test pattern generating unit according to claim 3, wherein said address generating module further receives specified address data issued by said sequence controller, and said specified address data and said second intermediate data and said Z-group first intermediate data are used as data sources to perform a second level logic operation to obtain third intermediate data.
5. The test pattern generating unit according to claim 1, wherein the address data includes X-group address data, Y-group address data, and Z-group register data, the address generating module receives first register data issued by the sequence controller, the first register data including X-group address maximum limit, Y-group address maximum limit, and third register data for performing a logical operation in combination with the X-group address data, the Y-group address data, and the immediate data, respectively, to generate the first intermediate data.
6. The test pattern generating unit according to claim 5, wherein the first register number performs a logical operation in combination with the X group address data, the Y group address data, and the immediate number, comprising: Selecting the data of the third register data and the X group address data/the Y group address data for logic operation, and outputting the data after logic operation and comparing the data with the X group address maximum limit value/the Y group address maximum limit value; If the data after the logic operation is larger than the maximum limit value of the X group address/the maximum limit value of the Y group address, subtracting the data after the logic operation from the maximum limit value of the X group address/the maximum limit value of the Y group address, taking the remainder as the first intermediate number of the X group/the first intermediate number of the Y group, and outputting carry data to participate in the logic operation of the data of the Y group address/the data of the Z group register; And if the data after the logic operation is smaller than the maximum limit value of the X group address/the maximum limit value of the Y group address, outputting the data after the logic operation as X group first intermediate number/Y group first intermediate number.
7. The test pattern generating unit according to claim 1, wherein the data generating module receives 2M sets of fourth register data issued by the sequence controller, each 2 sets of fourth register data are respectively logically operated in combination with an immediate, and 2 sets of fourth intermediate data are generated to form 1-way fourth intermediate data, and the fourth register data include register assignment data and/or a last logical operation value.
8. The test pattern generating unit according to claim 7, wherein the data generating module further receives a zero value issued by the sequence controller, and performs a logical operation of M ways by using M-way fourth intermediate data and the fifth register data issued by the sequence controller as data sources, and the method comprises: Selecting first leading edge intermediate data and first trailing edge intermediate data based on the fourth intermediate data; Each path of the first front edge intermediate data and the first back edge intermediate data respectively carry out first-stage logic operation with the zeroing value as a data source to obtain fifth intermediate data, wherein the zeroing value is used for directly zeroing output; and the fifth intermediate data and the fifth register data are logically operated to output the operated leading edge data LDATA1 and the operated trailing edge data TDATA1.
9. The test pattern generating unit according to claim 8, wherein the fifth register includes flip data and DBI comparison data, the fifth intermediate data logically operates with the fifth register data to output operated-on leading edge data LDATA1 and operated-on trailing edge data TDATA1, comprising: and after the first front edge intermediate data and the first back edge intermediate data are respectively logically operated with the turning data, respectively carrying out data bus turning operation on operation results and the DBI comparison data, and outputting operated front edge data LDATA1 and operated back edge data TDATA1.
10. The test pattern generating unit according to claim 9, wherein the data generating module compares the received operation result with the DBI comparison data, and if the number of addresses 1 in the operation result is greater than the data bit width/2, the received operation result is completely inverted, and the calculated leading edge data LDATA1 and the calculated trailing edge data TDATA1 are output.
11. The test pattern generating device is characterized by comprising the test pattern generating unit, an output enabling data module, a comparison enabling data module and a multiplexer, wherein the test pattern generating unit, the output enabling data module, the comparison enabling data module and the multiplexer are any one of claims 1-10, the output enabling data module is connected with the sequence controller, the comparison enabling data module is connected with the sequence controller, the multiplexer is connected with the signal mapping module, the output enabling data module, the comparison enabling data module and the time sequence module, and the time sequence module is connected to a device to be tested through a PE chip; The output enabling data module performs enabling output or disabling output according to the output enabling parameters issued by the sequence controller, and the comparison enabling data module performs comparison output or disabling comparison output according to the comparison enabling parameters issued by the sequence controller; The multiplexer is used for gating output to the time sequence module, wherein the enabling output or the disabling output, the comparing output or the not comparing output and the physical mapped address and data output by the signal mapping module.

Description

Test pattern generation unit and test pattern generation device Technical Field The present application relates to the field of semiconductor testing technology, and in particular, to a test pattern generating unit and a test pattern generating device. Background The automatic semiconductor test refers to the detection of various parameter indexes of a device (Device Under Test, DUT) to be tested by using automatic test equipment (Automatic Test Equipment, ATE) and the rejection of defective products to control the factory quality of the semiconductor device. The resource board card of the tester is responsible for generating corresponding test signals according to the test pattern information and sending the test signals to the device to be tested, and how to adapt the waveform generation data of the resource board card to different test requirements is a problem to be solved urgently. Disclosure of Invention Based on this, it is necessary to provide a test pattern generating unit and a test pattern generating device that can accommodate different test requirements in view of the above-described problems. The application relates to a test pattern generating unit, which comprises a sequence controller, an address generating module, a data generating module and a signal mapping module, wherein the signal mapping module is used for synchronously receiving M paths of operated addresses and M paths of operated data, outputting the physically mapped addresses and data, and M is more than or equal to 1; The address generation module respectively carries out logic operation on address data issued by the sequence controller by combining immediate data to obtain first intermediate data, the first intermediate data carries out M paths of logic operation by combining second register data issued by the sequence controller as a data source to output M paths of post-operation addresses, each path of post-operation address comprises a front edge post-operation address and a back edge post-operation address, the data generation module respectively carries out logic operation on fourth register data issued by the sequence controller by combining immediate data to obtain M paths of fourth intermediate data, the M paths of fourth intermediate data and the fifth register data issued by the sequence controller are used as data sources to carry out M paths of logic operation, and each path of post-operation data comprises front edge post-operation data and back edge post-operation data. In one embodiment, the address data includes X-group address data, Y-group address data, and Z-group register data, where the address data is logically operated by combining with an immediate data to obtain first intermediate data, where the first intermediate data includes X-group first intermediate data, Y-group first intermediate data, and Z-group first intermediate data, and the first intermediate data and the second register data are used as data sources to perform M-way logic operation, where each way of logic operation includes three-level logic operations. In one embodiment, each path of logic operation comprises three stages of logic operations, including: The first intermediate data of the X groups, the first intermediate data of the Y groups and the first intermediate data of the Z groups are used as data sources to carry out first-stage logic operation, so as to obtain second intermediate data; the second intermediate data and the Z groups of first intermediate data are used as data sources to carry out second-stage logic operation, and third intermediate data are obtained; And performing third-stage logic operation by taking the third intermediate data and the second register data as data sources to obtain a front edge operated address and a rear edge operated address. In one embodiment, the address generating module further receives designated address data sent by the sequence controller, and the designated address data, the second intermediate data and the first intermediate data of the Z groups are used as data sources to perform second-level logic operation, so as to obtain third intermediate data. In one embodiment, the address data includes X-group address data, Y-group address data, and Z-group register data, and the address generation module receives first register data issued by the sequence controller, where the first register data includes an X-group address maximum limit value, a Y-group address maximum limit value, and third register data, and is configured to perform logic operation in combination with the X-group address data, the Y-group address data, and the immediate data, respectively, to generate the first intermediate data. In one embodiment, the first register number performs a logical operation in combination with the X group address data, the Y group address data, and the immediate, including: Selecting the data of the third register data and the X group address data/the Y group address data for logic operatio