CN-122018855-A - Test pattern generating device, resource board card and tester

CN122018855ACN 122018855 ACN122018855 ACN 122018855ACN-122018855-A

Abstract

The application relates to a test pattern generating device, a resource board card and a testing machine, wherein the test pattern generating device comprises a sequence controller, an address generating module, a data generating module, a delay module and a signal mapping module, wherein the sequence controller is used for respectively issuing corresponding data signals and control signals, the address generating module is used for carrying out multi-path address selection operation on received data signals according to the received control signals and outputting multi-path operation addresses to the delay module, the data generating module is used for carrying out multi-path data selection operation on the received data signals according to the received control signals and outputting multi-path operation data to the delay module, the delay module is used for delaying the multi-path operation addresses and the multi-path operation data and then sending the delayed multi-path operation data to the signal mapping module, and the signal mapping module is used for selecting multi-path designated physical mapped addresses and data output from the multi-path operation addresses and the multi-path operation data according to the received control signals, so that the data quantity generated by a test pattern is increased and the test efficiency is improved.

Inventors

ZHANG SHUANGYANG
CHEN JUN
REN WENJUN
HOU QIONG
WEI SHILONG
XU JIAN
Ai Xueqian

Assignees

长迈半导体(成都)有限公司

Dates

Publication Date: 20260512
Application Date: 20251219

Claims (18)

1. A test pattern generating apparatus, comprising: the sequence controller is connected with the address generation module, the data generation module and the signal mapping module and is used for respectively issuing corresponding data signals and control signals; The address generation module is connected with the delay module and is used for carrying out multi-path address selection operation on the received data signals according to the received control signals and outputting the addresses after the multi-path operation to the delay module; the data generation module is connected with the delay module and is used for carrying out multi-path data selection operation on the received data signals according to the received control signals and outputting the multi-path operated data to the delay module; The delay module is connected with the signal mapping module and is used for delaying the addresses after the multi-path operation and the data after the multi-path operation and then sending the addresses and the data to the signal mapping module; the signal mapping module is used for selecting a plurality of designated physical mapped addresses and data from the addresses after the multi-path operation and the data after the multi-path operation according to the received control signals and outputting the selected physical mapped addresses and the data; The address generating module, the data generating module and the time delay module all receive the output data of the last module and the control signal issued by the sequence controller at the same time, and correspondingly process the output data of the last module based on the received control signal.
2. The device for generating test patterns according to claim 1, wherein the address generation module receives N paths of address data issued by the sequence controller, each path of address data comprises X sets of address data, Y sets of address data and Z sets of register data, each path of address data is respectively combined with an immediate to perform logic operation to obtain N paths of first intermediate data, the address generation module is further combined with the N paths of first intermediate data and the second register data issued by the sequence controller to perform logic operation of M paths as a data source, each path of address data outputs two sets of addresses after operation, wherein when N is equal to 1, M is greater than N, and when N is greater than 1, M is greater than or equal to N.
3. The test pattern generating device according to claim 2, wherein the address generating module receives N paths of first register data issued by the sequence controller, each path of first register data including X sets of address maximum limit values, Y sets of address maximum limit values, and third register data, and is configured to perform logic operation in combination with the X sets of address data, the Y sets of address data, and the immediate data in the corresponding path of address data, respectively, to generate the first intermediate data in the corresponding path.
4. A test pattern generating apparatus according to claim 3, wherein each of said first register numbers performs a logical operation in combination with said X group address data, said Y group address data, and said immediate data in the corresponding way of said address data, comprising: Selecting the data of the third register data and the X group address data/the Y group address data for logic operation, and outputting the data after logic operation and comparing the data with the X group address maximum limit value/the Y group address maximum limit value; If the data after the logic operation is larger than the maximum limit value of the X group address/the maximum limit value of the Y group address, subtracting the data after the logic operation from the maximum limit value of the X group address/the maximum limit value of the Y group address, taking the remainder as the first intermediate number of the X group address/the first intermediate number of the Y group address, and outputting carry data to participate in the logic operation of the Y group address data/the Z group register data; And if the data after the logic operation is smaller than the maximum limit value of the X group address/the maximum limit value of the Y group address, outputting the data after the logic operation as the first intermediate number of the X group address/the first intermediate number of the Y group address.
5. The test pattern generating apparatus according to any one of claims 2 to 4, wherein the address generating module performs each logical operation by combining the second register data, the N sets of first intermediate data, and the second intermediate data for each two logical operations as data sources, each outputting two sets of post-operation addresses.
6. The test pattern generating apparatus according to claim 5, wherein said address generating module sequentially performs the logical operations of each path by combining the second intermediate data of each two paths of the logical operations and said second register data, said N sets of the first intermediate data as data sources when the total number of logical operations M is even, and sequentially performs the logical operations of M-1 paths by combining the second intermediate data of each two paths of the logical operations and said second register data, said N sets of the first intermediate data as data sources and performs the logical operations of the M-1 paths by combining said second register data, said N sets of the first intermediate data as data sources when the total number of logical operations M is odd.
7. The test pattern generating device according to any one of claims 2 to 4, wherein when N is equal to 1, the address generating module performs two logic operations on the first intermediate data RXA-RXH, the first intermediate data RYA-RYH, and the first intermediate data RZA-RZE as data sources in one logic operation, respectively, to obtain second intermediate data XS1 and second intermediate data YS1, performs two logic operations on the second intermediate data XS1, the second intermediate data YS1, the first intermediate data RZA-RZE, and the second intermediate data XS2 and the second intermediate data YS2 of the other logic operation as data sources, respectively, to obtain third intermediate data XT and third intermediate data YT, performs two logic operations on the third intermediate data YT, and the corresponding second register data, respectively, and outputs the post-operation address X1 and the post-operation address Y1; The first intermediate data RXA-RXH is intermediate data obtained by combining the immediate and the X-group address data for logic operation, and the first intermediate data RYA-RYH is intermediate data obtained by combining the immediate and the Y-group address data for logic operation.
8. The device according to claim 7, wherein the address generation module performs the logic operation twice with the second intermediate data XS1, the second intermediate data YS1, the first intermediate data RZA-RZE, the second intermediate data XS2 of another logic operation, the second intermediate data YS2, and the configured specified address data as data sources, respectively, to obtain the third intermediate data XT and the third intermediate data YT.
9. The test pattern generating device according to claim 1, wherein the data generating module performs a logic operation on the 2M sets of fourth register data issued by the sequence controller in combination with the immediate data, respectively, to obtain 2M sets of fourth intermediate data, and performs a logic operation on M paths of data sources in combination with the 2M sets of fourth intermediate data and the fifth register data issued by the sequence controller, each path outputting two sets of post-operation data.
10. The test pattern generating device according to claim 9, wherein each 2 sets of fourth register data are logically operated in combination with an immediate data, respectively, to generate 2 sets of fourth intermediate data to constitute 1-way fourth intermediate data, and wherein said data generating module further performs M-way logical operation in combination with each two-way fourth intermediate data and the corresponding fifth register data as data sources, to output two sets of post-operation data for each way.
11. The device according to claim 10, wherein the data generating module sequentially performs the logic operation of each path by combining every two paths of the fourth intermediate data and the corresponding fifth register data as the data source when the total number of the logic operation paths M is even, and sequentially performs the logic operation of M-1 paths by combining every two paths of the fourth intermediate data and the corresponding fifth register data as the data source when the total number of the logic operation paths M is odd, and then performs the logic operation of the Mth path by combining the Mth path of the fourth intermediate data and the corresponding fifth register data as the data source.
12. The test pattern generating apparatus according to claim 9, wherein the fifth register data includes flip data and DBI comparison data, first leading edge intermediate data and first trailing edge intermediate data are selected based on fourth intermediate data, and after the first leading edge intermediate data and the first trailing edge intermediate data are logically operated with the flip data, respectively, the operation results are subjected to data bus flip operation with the DBI comparison data, respectively, and the operated leading edge data LDATA1 and the operated trailing edge data TDATA1 are output.
13. The test pattern generating device according to claim 12, wherein the data generating module compares the received operation result with the DBI comparison data, and if the number of addresses 1 in the operation result is greater than the data bit width/2, then the received operation result is completely inverted, and the calculated leading edge data LDATA1 and the calculated trailing edge data TDATA1 are output.
14. The test pattern generating apparatus according to claim 1, further comprising: The first verification module is connected with the address generation module and the delay module and is used for verifying the received operated address according to the received control signal and outputting the address information after multipath processing to the delay module; The second checking module is connected with the data generating module and the time delay module and is used for checking the received calculated data according to the received control signal and outputting the data information after multipath processing to the time delay module; The first checking module and the second checking module both receive the output data of the previous module and the control signal issued by the sequence controller at the same time, and correspondingly process the output data of the previous module based on the received control signal; The signal mapping module selects multiple designated physical mapped addresses and data from the multiple processed address information and the multiple processed data information according to the received control signals and outputs the multiple designated physical mapped addresses and data.
15. The test pattern generating device according to claim 1, comprising a first test pattern generating module and a second test pattern generating module; The first test pattern generation module comprises the sequence controller, the address generation module, the data generation module, the delay module, the signal mapping module, a comparison enabling parameter delay module and an output enabling parameter delay module, wherein the comparison enabling parameter delay module and the output enabling parameter delay module are connected with the sequence controller; The second test pattern generation module comprises an output enabling data module, a comparison enabling data module and a multiplexer, wherein the output enabling data module is connected with the output enabling parameter delay module, the comparison enabling data module is connected with the comparison enabling parameter delay module, the multiplexer is connected with the signal mapping module, the output enabling data module, the comparison enabling data module and a time sequence module, and the time sequence module is connected to a device to be tested through a PE chip; The output enabling parameter delay module is used for delaying the output enabling parameters of the corresponding paths issued by the sequence controller and then transmitting the delayed output enabling parameters to the output enabling data module, the comparison enabling parameter delay module is used for delaying the comparison enabling parameters of the corresponding paths issued by the sequence controller and then transmitting the delayed comparison enabling parameters to the comparison enabling data module, and the output enabling data module performs enabling output or disabling output according to the received output enabling parameters; The multiplexer is used for gating and outputting all paths of enabling output or disabling output, all paths of comparing output or disabling output and all paths of physically mapped addresses and data output by the signal mapping module to the time sequence module.
16. The test pattern generating device of claim 15, wherein the first test pattern generating module further comprises a specified data parameter delay module, the second test pattern generating module further comprises a specified data module and a graphics data storage module, the specified data parameter delay module connects the sequence controller and the specified data module, and the multiplexer connects the specified data module and the graphics data storage module; The specified data parameter delay module is used for delaying the specified data parameters of the corresponding paths issued by the sequence controller and then transmitting the delayed specified data parameters to the specified data module, the specified data module selects the specified data of the corresponding paths from preset data according to the received specified data parameters and transmits the selected specified data to the multiplexer, and the multiplexer outputs all paths of enabling output or disabling output, all paths of comparing output or not comparing output, all paths of addresses and data after physical mapping, all paths of specified data and preset graphic data in the graphic data storage module to the time sequence module in a gating manner.
17. The resource board card is characterized by comprising a time sequence module, a PE chip and the test pattern generating device in any one of claims 1 to 16, wherein the time sequence module carries out waveform conversion and waveform change delay according to received data and then outputs the waveform conversion and waveform change delay to the PE chip, and samples and compares signals returned by the PE chip according to comparison expected values at comparison time according to comparison enabling time to obtain a comparison result and stores the comparison result in a storage module.
18. A test machine comprising the resource board card of claim 17.

Description

Test pattern generating device, resource board card and tester Technical Field The present application relates to the field of semiconductor testing technology, and in particular, to a test pattern generating device, a resource board card, and a testing machine. Background The automatic semiconductor test refers to the detection of various parameter indexes of a device (Device Under Test, DUT) to be tested by using automatic test equipment (Automatic Test Equipment, ATE) and the rejection of defective products to control the factory quality of the semiconductor device. The resource board card of the tester is responsible for generating corresponding test signals according to the test pattern information and sending the corresponding test signals to the device to be tested, and the current data generating rate of the waveform of the resource board card cannot meet the test rate requirement because the test rate of the tester is higher and higher. How to improve the test efficiency is a problem to be solved urgently. Disclosure of Invention In view of the above, it is desirable to provide a test pattern generating device, a resource board, and a tester that can improve test efficiency. A first aspect of the present application provides a test pattern generating apparatus comprising: the sequence controller is connected with the address generation module, the data generation module and the signal mapping module and is used for respectively issuing corresponding data signals and control signals; The address generation module is connected with the delay module and is used for carrying out multi-path address selection operation on the received data signals according to the received control signals and outputting the addresses after the multi-path operation to the delay module; the data generation module is connected with the delay module and is used for carrying out multi-path data selection operation on the received data signals according to the received control signals and outputting the multi-path operated data to the delay module; The delay module is connected with the signal mapping module and is used for delaying the addresses after the multi-path operation and the data after the multi-path operation and then sending the addresses and the data to the signal mapping module; the signal mapping module is used for selecting a plurality of designated physical mapped addresses and data from the addresses after the multi-path operation and the data after the multi-path operation according to the received control signals and outputting the selected physical mapped addresses and the data; The address generating module, the data generating module and the time delay module all receive the output data of the last module and the control signal issued by the sequence controller at the same time, and correspondingly process the output data of the last module based on the received control signal. In one embodiment, the address generating module receives N paths of address data issued by the sequence controller, each path of address data comprises X sets of address data, Y sets of address data and Z sets of register data, each path of address data is combined with an immediate to perform logic operation to obtain N paths of first intermediate data, the address generating module further combines the N paths of first intermediate data and second register data issued by the sequence controller to perform logic operation of M paths, each path of address data outputs two sets of addresses after operation, wherein when N is equal to 1, M is greater than N, and when N is greater than 1, M is greater than or equal to N. In one embodiment, the address generating module receives N paths of first register data issued by the sequence controller, where each path of first register data includes an X-group address maximum limit value, a Y-group address maximum limit value, and a third register data, and is configured to perform a logic operation by respectively combining the X-group address data, the Y-group address data, and the immediate data in the corresponding path of address data, to generate the first intermediate data of the corresponding path. In one embodiment, each way of the first register number performs a logic operation in combination with the X group address data, the Y group address data, and the immediate within the corresponding way of the address data, including: Selecting the data of the third register data and the X group address data/the Y group address data for logic operation, outputting the data after logic operation and comparing with the maximum limit value of the X group address/the maximum limit value of the Y group address, If the data after the logic operation is larger than the maximum limit value of the X group address/the maximum limit value of the Y group address, subtracting the data after the logic operation from the maximum limit value of the X group address/the maximum limit value of the Y group add