CN-122018885-A - Simulink code generation method and device based on hardware instruction

CN122018885ACN 122018885 ACN122018885 ACN 122018885ACN-122018885-A

Abstract

The application provides a Simulink code generation method and device based on a hardware instruction, and relates to the technical field of embedded code generation, wherein the method comprises the steps of obtaining an initial data flow diagram of a model, and reconstructing the initial data flow diagram based on a preset optimization rule to obtain a reconstructed target data flow diagram; analyzing the topology structure of the reconstructed data flow graph, determining the execution dependency relationship among the components, deducing a code translation sequence, respectively generating code segments corresponding to each component in the code translation sequence, and integrating the generated code segments according to the code translation sequence indicated by the code translation sequence to obtain the target code. The code generation method and the code generation device provided by the application can select the candidate rule capable of maximizing the delay reduction to identify the optimizable component in the code generation process, and comprehensively generate the corresponding hardware specific instruction for the optimizable component, so that the high-efficiency embedded code capable of being directly deployed is produced.

Inventors

YU ZEHONG
SU ZHUO
Pu Jinxiao
SHI DALONG
JIANG YU

Assignees

清华大学
中航国际金网(北京)科技有限公司

Dates

Publication Date: 20260512
Application Date: 20251224

Claims (10)

1. The Simulink code generation method based on the hardware instruction is characterized by comprising the following steps of: acquiring an initial data flow diagram of a target Simulink model, and reconstructing the initial data flow diagram based on a preset optimization rule to obtain a reconstructed target data flow diagram, wherein the optimization rule is used for reducing the execution time delay of a hardware instruction; Performing topological structure analysis on the target data flow graph, determining execution dependency relationships among components, and deducing a code translation sequence based on the execution dependency relationships among the components; Generating code segments corresponding to each component respectively, and integrating the generated code segments according to a code translation sequence indicated by a code translation sequence to obtain a target code; The components in the target data flow graph comprise an optimizable component and a basic component, wherein code fragments corresponding to the optimizable component are hardware instructions, and code fragments corresponding to the basic component are executable functional codes.
2. The method of claim 1, wherein reconstructing the initial dataflow graph based on the preset optimization rule to obtain a reconstructed target dataflow graph includes: acquiring a plurality of available optimization rules and an evaluation result of each available optimization rule, wherein the evaluation result is used for representing the delay reduction amplitude of executing a hardware instruction; based on the evaluation result of each available optimization rule, carrying out iterative updating on the initial data flow graph until the reconstructed target data flow graph is obtained; The iterative updating comprises the steps of screening out an optimal rule capable of maximally reducing execution time delay from the plurality of available optimal rules by using a time delay sensitive method, and reconstructing the initial data flow diagram by using the optimal rule.
3. The method of claim 2, wherein the obtaining a plurality of available optimization rules and the evaluation result of each available optimization rule comprises: Determining a deployment platform of the target code, and screening a plurality of available optimization rules matched with the deployment platform of the target code from preset optimization rules in a rule base; And evaluating each available optimization rule in the plurality of available optimization rules to obtain an evaluation result of each available optimization rule.
4. The method of claim 2, wherein iteratively updating the initial dataflow graph based on the evaluation result of each available optimization rule until the reconstructed target dataflow graph is obtained, includes: Determining available optimization rules applicable to each component based on the matching results of the available optimization rules and the applicability of the initial data flow graph respectively to obtain a plurality of candidate rules, and determining an execution delay reduction value of each candidate rule based on the evaluation result of each candidate rule; Screening an optimal rule for reconstructing the data flow graph from the plurality of candidate rules by using a preset screening method, and updating the data flow graph based on the screened optimal rule until the reconstructed target data flow graph is obtained; The preset screening method comprises the steps of updating a current delay reduction value based on the execution delay reduction value of any target candidate rule in the plurality of candidate rules if the execution delay reduction value of the target candidate rule is larger than the current maximum delay reduction value, and determining the target candidate rule as an optimal rule.
5. The method of claim 4, wherein each of the plurality of optimization rules is represented in a dataflow graph sub-graph; updating the data flow graph based on the screened optimal rule until the reconstructed target data flow graph is obtained, wherein the updating comprises the following steps: Packaging the data flow graph subgraph into a new component based on an input port and an output port of a target data flow graph subgraph for representing the optimal rule; And allocating corresponding functional attributes for the new component, and marking the new component as an optimizable component.
6. The method according to claim 1, wherein the generating code segments corresponding to each component respectively includes: For the optimizable components, matching hardware characteristic instructions corresponding to each optimizable component based on the deployment platform of the target code, the component function and the data type of each optimizable component; and generating assembly codes corresponding to the optimizable components based on the hardware characteristic instructions corresponding to the optimizable components, and mapping the assembly code input/output data corresponding to the optimizable components to the input/output ports of the optimizable components.
7. The method according to claim 1, wherein the generating code segments corresponding to each component respectively includes: for the base components, corresponding function code is generated based on the component functions of each base component.
8. The method according to any one of claims 1 to 7, wherein integrating the generated code fragments in the code translation order indicated by the code translation sequence to obtain the target code comprises: and integrating the code segments corresponding to each optimizable component and the code segments corresponding to each basic component, and integrating the generated code segments according to the code translation sequence to obtain the target code.
9. A Simulink code generation apparatus based on hardware instructions, the apparatus comprising: The data flow diagram reconstruction module is used for acquiring an initial data flow diagram of the target Simulink model, and reconstructing the initial data flow diagram based on a preset optimization rule to obtain a reconstructed target data flow diagram, wherein the optimization rule is used for reducing the execution time delay of a hardware instruction; The code generation module is used for performing topological structure analysis on the target data flow graph, determining the execution dependency relationship among the components and deducing a code translation sequence based on the execution dependency relationship among the components; The code generation module is further used for respectively generating code segments corresponding to each component, and integrating the generated code segments according to a code translation sequence indicated by the code translation sequence to obtain an object code; The components in the target data flow graph comprise an optimizable component and a basic component, wherein code fragments corresponding to the optimizable component are hardware instructions, and code fragments corresponding to the basic component are executable functional codes.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the Simulink code generation method based on hardware instructions as claimed in any one of claims 1 to 8 when the program is executed.

Description

Simulink code generation method and device based on hardware instruction Technical Field The application relates to the technical field of embedded code generation, in particular to a Simulink code generation method and device based on hardware instructions. Background Simulinl is a key tool for Model-driven development (MDD), which has become a cornerstone in safety-critical system engineering, such as automotive systems, aerospace systems, and medical systems. The complex system behavior is abstracted into a high-level model, so that the production efficiency, the reliability and the maintainability of development are improved. Code generation plays a vital role in model-driven development, and it can automatically convert a high-level model into embedded code, thereby reducing the manual effort and coding errors. Since embedded devices typically have low power consumption and high real-time characteristics, applications must meet specific power consumption and performance goals. Based on this, a code generation scheme is needed, which can reduce the execution delay of the hardware instruction and improve the performance of the whole code. Disclosure of Invention The application aims to provide a Simulink code generation method and device based on hardware instructions, which can select candidate rules capable of maximizing delay reduction to identify optimizable components in the code generation process, and comprehensively generate corresponding hardware specific instructions for the optimizable components, so that high-efficiency embedded codes capable of being deployed directly are produced. The application provides a Simulink code generation method based on a hardware instruction, which comprises the following steps: The method comprises the steps of obtaining an initial data flow diagram of a target Simulink model, reconstructing the initial data flow diagram based on a preset optimization rule to obtain a reconstructed target data flow diagram, wherein the optimization rule is used for reducing execution time delay of hardware instructions, executing topological structure analysis on the target data flow diagram, determining execution dependency relationships among components, deriving code translation sequences based on the execution dependency relationships among the components, respectively generating code fragments corresponding to each component, and integrating the generated code fragments according to the code translation sequences indicated by the code translation sequences to obtain target codes, wherein the components in the target data flow diagram comprise an optimizable component and a basic component, the code fragments corresponding to the optimizable component are hardware instructions, and the code fragments corresponding to the basic component are executable functional codes. The method comprises the steps of obtaining a plurality of available optimization rules and an evaluation result of each available optimization rule, wherein the evaluation result is used for representing the time delay reduction amplitude of an execution hardware instruction, and based on the evaluation result of each available optimization rule, carrying out iterative updating on the initial data flow graph until the target data flow graph after being reconstructed is obtained, wherein the iterative updating comprises the steps of screening out an optimal rule capable of maximally reducing the execution time delay from the plurality of available optimization rules by using a time delay sensitive method, and carrying out reconstruction on the initial data flow graph by using the optimal rule. Optionally, the obtaining a plurality of available optimization rules and an evaluation result of each available optimization rule includes determining a deployment platform of the target code, screening a plurality of available optimization rules matched with the deployment platform of the target code from preset optimization rules in a rule base, and evaluating each available optimization rule in the plurality of available optimization rules to obtain an evaluation result of each available optimization rule. The method comprises the steps of determining available optimization rules applicable to each component based on the matching result of the available optimization rules and the applicability of the initial data flow graph respectively to obtain a plurality of candidate rules, determining an execution delay reduction value of each candidate rule based on the evaluation result of each candidate rule, screening out optimal rules for data flow graph reconstruction from the plurality of candidate rules by using a preset screening method, and updating the data flow graph based on the screened optimal rules until the target data flow graph after reconstruction is obtained, wherein the preset screening method comprises the steps of updating the current delay reduction value based on the execution delay reduction value of