CN-122018920-A - Binary translation optimization method, binary translator and electronic equipment

Abstract

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, wherein the binary translation optimization method comprises the steps of updating a state mark of a first register in a preset state table according to a write bit width of a first register when translating a narrow write operation instruction, wherein the state mark is used for indicating whether a high bit of a corresponding register needs to be cleared or not and recording the valid bit width of the corresponding register, acquiring a state mark of a second register corresponding to a read operation from the preset state table when translating the read operation instruction, inserting a first clear instruction before a translation result of the read operation instruction if the read bit width of the read operation is larger than the valid bit width indicated by the state mark of the second register, and clearing the appointed high bit of the second register by the first clear instruction. The invention can simplify the target machine code sequence generated by translation, greatly reduce redundant operation and improve the execution efficiency of a translation system.

Inventors

• HE ZIHAN
• ZENG LU

Assignees

• 龙芯中科技术股份有限公司

Dates

Publication Date

20260512

Application Date

20260409

Claims (10)

1. 1. A binary translation optimization method, the method comprising: When translating to a narrow write operation instruction, updating a state mark of a first register in a preset state table according to the write bit width of the first register by the narrow write operation, wherein the state mark of each register in an active architecture is recorded in the preset state table and is used for indicating whether the high bit of the corresponding register needs to be cleared or not and recording the valid bit width of the corresponding register; When translating to a read operation instruction, acquiring a state mark of a second register corresponding to the read operation from the preset state table; If the read bit width of the read operation is larger than the valid bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the read operation instruction, and the first zero clearing instruction is used for zero clearing the appointed high bit of the second register.
2. 2. The method according to claim 1, wherein the method further comprises: traversing the preset state table when translating to a control flow transfer point, and judging whether a register to be cleared exists or not according to a state mark corresponding to each register; if the register to be cleared exists, determining a target position according to the control flow transfer point; Inserting a second zero clearing instruction into the target position, wherein the second zero clearing instruction is used for zero clearing the designated high bit of the register to be zero cleared.
3. 3. The method of claim 2, wherein said determining a target location from said control flow transfer point comprises: If the control flow is transferred to active transfer, determining the target position as the front of the translation result of the boundary instruction of the current code block, wherein the boundary instruction comprises a jump instruction, a function call instruction or a function return instruction, or And if the control flow is transferred to the passive transfer, determining that the target position is after the translation result of the last normal instruction before the context save instruction, wherein the passive transfer comprises exception handling, interrupt response or context switching.
4. 4. The method according to claim 1, wherein the method further comprises: Initializing the preset state table to set the state marks of all registers in the preset state table to be initial state, wherein the initial state represents that high bits are not cleared.
5. 5. The method according to claim 1, wherein the method further comprises: and when translating to a full-width write operation instruction, setting a state mark of a third register corresponding to the full-width write operation in the preset state table to be an initial state.
6. 6. The method of any one of claims 1 to 5, wherein the narrow write operation includes writing the S register or the D register in scalar form and writing the vector register in a narrow vector form other than 128 bits wide.
7. 7. The method of any one of claims 1 to 5, wherein the specified high-order bits refer to a remaining high-order bit portion of the register other than the low-order bit occupied by the valid data.
8. 8. A binary translator, characterized in that, the binary translator includes: The state updating module is used for updating the state mark of the first register in a preset state table according to the writing bit width of the first register when translating to the narrow writing operation instruction, wherein the state mark of each register in the active architecture is recorded in the preset state table and is used for indicating whether the high bit of the corresponding register needs to be cleared or not and recording the valid bit width of the corresponding register; The state acquisition module is used for acquiring a state mark of a second register corresponding to the read operation from the preset state table when translating to the read operation instruction; And the first processing module is used for inserting a first zero clearing instruction before the translation result of the read operation instruction if the read bit width of the read operation is larger than the valid bit width indicated by the state mark of the second register, and the first zero clearing instruction is used for clearing the appointed high bit of the second register.
9. 9. The binary translator of claim 8, wherein the binary translator further comprises: the state table traversing module is used for traversing the preset state table when translating to a control flow transfer point, and judging whether a register to be cleared exists or not according to the state mark corresponding to each register; The position determining module is used for determining a target position according to the control flow transfer point if the register to be cleared exists; The second zero clearing instruction is used for zero clearing the appointed high-order of the register to be zero cleared.
10. 10. An electronic device comprising a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface are in communication with each other via the communication bus, and wherein the memory is configured to store at least one executable instruction that causes the processor to perform the steps of the binary translation optimization method according to any one of claims 1 to 7.

Description

Binary translation optimization method, binary translator and electronic equipment Technical Field The present invention relates to the field of computer technologies, and in particular, to a binary translation optimization method, a binary translator, and an electronic device. Background Binary translation may convert a source program running on one architecture platform to a target program running on another architecture platform to solve the problem of application running across instruction set architectures at the binary level. Binary translation is one of the research hotspots in the field of computer technology in recent years. In the AArch64 architecture instruction set, 128-bit vector registers (V0-V31) are used for both scalar floating point operations and SIMD (Single Instruction Multiple Data, single instruction multiple data stream) vector operations. The specification forces that when an instruction writes to a target register in a narrow write form (i.e., a write width of less than 128 bits), the unreached high order bits in the target register must be cleared immediately. When the LoongArch, RISC-V architecture processes such narrow write operation, the high-order original value is reserved by default or sign expansion is adopted, and zero clearing is not forced. In order to eliminate the semantic difference and ensure the correctness of binary translation, the traditional dynamic binary translator adopts an immediate physical zero clearing strategy, namely, after each translation of the narrow write operation instruction of the AArch64 architecture, a zero clearing instruction (such as a bitwise AND, insertion or special zero extension instruction and the like operation instruction) is additionally generated for forcedly clearing the high bit of the target register. However, in vector intensive practical application scenarios such as audio and video encoding and decoding, machine learning, scientific computing and the like, the same register is often executed for a plurality of times, and a zero clearing instruction is generated for each narrow writing operation by the zero clearing strategy, so that target code expansion and redundant operation are increased, and the execution efficiency of a translation system is affected. Disclosure of Invention In view of the above problems, embodiments of the present invention are provided to provide a binary translation optimization method for overcoming the above problems or at least partially solving the above problems, which can simplify a target machine code sequence generated by translation, greatly reduce redundant operations, and improve execution efficiency of a translation system. Correspondingly, the embodiment of the invention also provides a binary translator and electronic equipment, which are used for ensuring the realization and application of the method. In a first aspect, an embodiment of the present invention discloses a binary translation optimization method, where the method includes: When translating to a narrow write operation instruction, updating a state mark of a first register in a preset state table according to the write bit width of the first register by the narrow write operation, wherein the state mark of each register in an active architecture is recorded in the preset state table and is used for indicating whether the high bit of the corresponding register needs to be cleared or not and recording the valid bit width of the corresponding register; When translating to a read operation instruction, acquiring a state mark of a second register corresponding to the read operation from the preset state table; If the read bit width of the read operation is larger than the valid bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the read operation instruction, and the first zero clearing instruction is used for zero clearing the appointed high bit of the second register. In a second aspect, embodiments of the present invention disclose a binary translator, the binary translator comprising: The state updating module is used for updating the state mark of the first register in a preset state table according to the writing bit width of the first register when translating to the narrow writing operation instruction, wherein the state mark of each register in the active architecture is recorded in the preset state table and is used for indicating whether the high bit of the corresponding register needs to be cleared or not and recording the valid bit width of the corresponding register; The state acquisition module is used for acquiring a state mark of a second register corresponding to the read operation from the preset state table when translating to the read operation instruction; And the first processing module is used for inserting a first zero clearing instruction before the translation result of the read operation instruction if the read