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CN-122018939-A - Upgrading method, device, equipment and computer readable storage medium

CN122018939ACN 122018939 ACN122018939 ACN 122018939ACN-122018939-A

Abstract

The invention discloses an upgrading method, a device, equipment and a computer readable storage medium, which are applied to the technical field of computers and comprise the steps of storing a logic device image when the logic device image is received, selecting a target processor core from a management controller with at least two or more processor cores, sending a storage address of the logic device image to the target processor core through inter-core communication, enabling a cache disabling mechanism to the target processor core and a memory area corresponding to the logic device image, configuring an upgrading task to be the highest execution priority and setting the highest execution priority to be forbidden to be scheduled, reading the logic device image through the storage address by using the target processor core, and burning the logic device image to the logic device through GPIO (general purpose input/output) analog JTAG (joint test action group) protocol to complete the upgrading task. The invention solves the core pain point of high failure rate of GPIO analog JTAG upgrading in the prior art, and realizes stable and efficient upgrading of the logic device mirror image.

Inventors

  • MA WENKAI

Assignees

  • 山东云海国创云计算装备产业创新中心有限公司

Dates

Publication Date
20260512
Application Date
20260130

Claims (10)

  1. 1. An upgrade method for a management controller having at least two or more processor cores, comprising: storing the logic device image when the logic device image is received, and selecting a target processor core from the management controller; Transmitting the storage address of the logic device mirror image to the target processor core through inter-core communication, enabling a cache disabling mechanism for the target processor core and a memory area corresponding to the logic device mirror image, and configuring an upgrading task as the highest execution priority and setting the upgrading task as forbidden scheduling; And reading the mirror image of the logic device by using the target processor core through the storage address, and burning the mirror image of the logic device to the logic device through a general input/output simulation joint test action group protocol to complete the upgrading task.
  2. 2. The upgrade method of claim 1, wherein storing the logical device image and selecting a target processor core from the management controller when the logical device image is received comprises: receiving the logic device image in an in-band and out-of-band upgrading mode, and storing the complete logic device image into a nonvolatile memory medium when the complete logic device image is received; one processor core is selected as the target processor core from the management controllers of at least two and more processor cores.
  3. 3. The upgrade method according to claim 1, further comprising, after storing the logical device image and selecting a target processor core from the management controller when the logical device image is received: Migrating the mirror image of the real-time operating system from the nonvolatile memory medium to the memory, and marking the memory attribute as a read-only attribute; Utilizing the target processor core to carry out integrity check on the mirror image of the real-time operating system in the memory; And if the verification is passed, executing the code of the real-time operating system by using the target processor core, wherein the target processor core enters a real-time operating system running mode.
  4. 4. The upgrade method of claim 3, wherein sending the memory address of the logical device image to the target processor core through inter-core communication, and enabling a cache disabling mechanism for the target processor core and the memory area corresponding to the logical device image, while configuring the upgrade task to be the highest execution priority and set to disable scheduling, comprises: after the real-time operating system of the target processor core normally operates, the storage address of the logic device mirror image in a nonvolatile memory medium is sent to the target processor core by utilizing a main processor core through an inter-core communication mode; And after the target processor core receives the storage address, marking the memory areas corresponding to the target processor core and the logic device mirror image as non-cacheable areas, and configuring the upgrading task of the logic device as the highest execution priority and setting the upgrading task as forbidden scheduling.
  5. 5. The upgrade method of claim 4, wherein after the target processor core is utilized to read the logic device image through the memory address and burn the logic device image to the logic device through the universal input output analog joint test action group protocol, the upgrade task is completed, further comprising: And sending the updated progress information to the main processor core by using the target processor core in an inter-core communication mode so that the main processor core displays the progress information.
  6. 6. The upgrade method of claim 4, wherein after the target processor core is utilized to read the logic device image through the memory address and burn the logic device image to the logic device through the universal input output analog joint test action group protocol, the upgrade task is completed, further comprising: and terminating the real-time operating system of the target processor core, and adding the target processor core to the scheduling of the main processor core.
  7. 7. The upgrade method of claim 1, further comprising: all processor cores of the management controller have the same control authority to the general input/output pins.
  8. 8. An upgrade apparatus for use with a management controller having at least two or more processor cores, comprising: The core determining module is used for storing the logic device mirror image when receiving the logic device mirror image, and selecting a target processor core from the management controller; the configuration module is used for sending the storage address of the logic device mirror image to the target processor core through inter-core communication, enabling a cache disabling mechanism for the target processor core and a memory area corresponding to the logic device mirror image, and simultaneously configuring an upgrading task as the highest execution priority and setting as forbidden scheduling; and the upgrading module is used for reading the logic device mirror image through the storage address by utilizing the target processor core, and burning the logic device mirror image to the logic device through a general input/output simulation joint test action group protocol to complete the upgrading task.
  9. 9. An upgrade apparatus, comprising: A memory for storing a computer program; A processor for implementing the upgrade method according to any one of claims 1 to 7 when executing the computer program.
  10. 10. A computer readable storage medium having stored therein computer executable instructions which when loaded and executed by a processor implement the upgrade method according to any one of claims 1 to 7.

Description

Upgrading method, device, equipment and computer readable storage medium Technical Field The present invention relates to the field of computer technologies, and in particular, to an upgrade method, apparatus, device, and computer readable storage medium. Background In the operation and maintenance of the server, the image upgrading of the logic device is realized through a management controller chip, and two main modes exist, namely, firstly, the management controller simulates JTAG (Joint Test Action Group, a standardized test method for testing the interconnection between chips on a circuit board) through GPIO (General-Purpose Input/Output, general IO for short) protocol burning image and triggers the system restart, and secondly, the management controller utilizes a hardware module with JTAG-MASTER (JTAG main module) to complete the burning and the restarting. However, both modes have defects that GPIO simulation mode is easily broken by other services, resulting in discontinuous JTAG time sequence and even upgrade failure, JTAG-MASTER hardware module is not completely suitable for JTAG-SLAVE (JTAG SLAVE) of all types of logic devices due to design solidification, and has insufficient compatibility. Therefore, how to consider the timing stability of the logic device upgrade and the compatibility of the multi-type logic device is a technical problem that needs to be solved currently. Disclosure of Invention Accordingly, an object of the present invention is to provide an upgrade method, apparatus, device and computer readable storage medium, which solve the problem that the upgrade of the logic device in the prior art cannot satisfy the timing stability and compatibility at the same time. In order to solve the above technical problems, the present invention provides an upgrade method applied to a management controller having at least two or more processor cores, including: storing the logic device image when the logic device image is received, and selecting a target processor core from the management controller; Transmitting the storage address of the logic device mirror image to the target processor core through inter-core communication, enabling a cache disabling mechanism for the target processor core and a memory area corresponding to the logic device mirror image, and configuring an upgrading task as the highest execution priority and setting the upgrading task as forbidden scheduling; And reading the mirror image of the logic device by using the target processor core through the storage address, and burning the mirror image of the logic device to the logic device through a general input/output simulation joint test action group protocol to complete the upgrading task. In one aspect, storing a logical device image when received and selecting a target processor core from the management controller includes: receiving the logic device image in an in-band and out-of-band upgrading mode, and storing the complete logic device image into a nonvolatile memory medium when the complete logic device image is received; one processor core is selected as the target processor core from the management controllers of at least two and more processor cores. In one aspect, after storing the logical device image and selecting the target processor core from the management controller when the logical device image is received, the method further comprises: Migrating the mirror image of the real-time operating system from the nonvolatile memory medium to the memory, and marking the memory attribute as a read-only attribute; Utilizing the target processor core to carry out integrity check on the mirror image of the real-time operating system in the memory; And if the verification is passed, executing the code of the real-time operating system by using the target processor core, wherein the target processor core enters a real-time operating system running mode. In one aspect, sending a storage address of the logic device image to the target processor core through inter-core communication, and enabling a cache disabling mechanism for the target processor core and a memory area corresponding to the logic device image, and simultaneously configuring an upgrade task to be a highest execution priority and set to be a forbidden schedule, including: after the real-time operating system of the target processor core normally operates, the storage address of the logic device mirror image in a nonvolatile memory medium is sent to the target processor core by utilizing a main processor core through an inter-core communication mode; And after the target processor core receives the storage address, marking the memory areas corresponding to the target processor core and the logic device mirror image as non-cacheable areas, and configuring the upgrading task of the logic device as the highest execution priority and setting the upgrading task as forbidden scheduling. In one aspect, after the target processor core is utilized to read the mirro