CN-122018970-A - Time sequence interference radar compiling and deploying method based on domestic ARM architecture

Abstract

The invention provides a method for native compiling and deploying time sequence interference radar processing tool chains ISCE and MintPy on a domestic ARM architecture. Aiming at three bottlenecks of poor compiling compatibility, difficult dependency library collaboration and huge virtualized computing power loss faced by the migration of x86 to ARM architecture, the method eliminates nonstandard path hard coding errors through a dynamic path repairing mechanism, establishes a mixed dependency scheduling system, solves incompatibility of symbol conflict and ABI, and deeply optimizes an instruction set to achieve performance maximization. Through strict verification, the compiling success rate is obviously improved from less than 50% to 100%, the calculation power utilization rate is 100%, the global first set of full-functional ARM time sequence InSAR processing system is successfully constructed, and the performance approaches to or even exceeds an x86 platform under the same hardware scale. The method is completely based on an open source scientific computing library, avoids commercial authorization cost, realizes a full-stack localization technology chain from a chip, an operating system to application software, and provides important localization technology support and multiple choices for satellite remote sensing deformation monitoring and geological disaster early warning.

Inventors

• WANG FENGMAO
• LI SHUANG
• LUO GUANGJIE
• WU JIANFENG
• YIN XUN
• WU XINGHUI
• YUAN QINGYANG
• LI YAN
• Ban Luwei

Assignees

• 贵州师范学院

Dates

Publication Date

20260512

Application Date

20260228

Claims (6)

1. 1. Through three major core technological breakthroughs of dynamic path repair, mixed dependent scheduling and instruction set deep optimization, a time sequence interference radar compiling and deploying method based on a domestic ARM architecture is constructed, high-performance lossless migration and deployment of ISCE and MintPy tool chains is realized, and the method is characterized in that: S1, taking an ARM (advanced RISC machine) native architecture system as a reference, referring to ISCE <2 > -MintPy tool chains to carry out migration compiling on the environment construction principle on an x86 architecture.
2. S2, integrating the environment by combining with Anaconda3, and implementing dynamic migration repair on the path.
3. And 3, S3, adopting a mixed dependency ecological system construction scheme to realize compiling, dependency and environment variable cooperative calling.
4. 4, S4, through deep optimization compiling of ARM architecture series instruction sets and a math library KML, the full-flow computing speed of ISCE-MintPy is effectively improved, and calculation power lossless conversion is achieved.
5. S5, outputting matrix verification result parameters through ISCE-MintPy collaborative deployment, comparing ARM with the x86 architecture operation time, further outputting a deformation rate inversion result graph, and optimizing scientific calculation quality verification.
6. S6, replacing server parameters, repeating the steps, and packaging, migrating and deploying ISCE-MintPy tool chain environments.

Description

Time sequence interference radar compiling and deploying method based on domestic ARM architecture Technical Field The invention relates to the field of geospatial science computation and artificial intelligence, in particular to a systematic method for deploying a time sequence interference radar processing tool chain on an ARM architecture domestic server. Background At present, with the rapid development of computer technology, the problem of China in the core technical field is also exposed. For such circumstances, domestic research and development has advanced a domestic series of servers based on the ARM architecture to provide high performance computing power. However, key tool chains ISCE and MintPy in the field of remote sensing science face outstanding challenges of architecture compatibility and performance optimization when migrating to the domestic ARM platform due to the highly bound x86 architecture of the design and the underlying layer, and are needed to perform ecological adaptation. Based on the method, the application provides a systemization method for deploying a time sequence interference radar processing tool chain on an ARM architecture domestic server. Disclosure of Invention Aiming at three technical bottlenecks of poor compiling compatibility, low dependency library collaborative scheduling and difficult computational power lossless conversion existing in the process of transferring the existing ISCE-MintPy tool chain from the x86 to the ARM architecture, the invention provides a whole set of efficient compiling and deploying method to partially solve the problems existing in the prior art. In order to achieve the above purpose, the following technical scheme is adopted in the specification: A time sequence interference radar compiling and deploying method based on a domestic ARM architecture comprises the following steps: According to national standards (GB/T11457-2006, GB/T35643-2017), based on domestic hardware characteristics and domestic operating system environments, three technical breakthroughs of dynamic path repair, mixed dependent scheduling and instruction set deep optimization are adopted, and the sequential interference radar processing tool chain is operated in a native and efficient mode of a non-x 86 architecture. S1, taking an ARM original architecture system as a reference, referring to ISCE < 2 > -MintPy tool chains to perform migration compiling on the environment construction principle on an x86 architecture, integrating the environment by combining with Anaconda3, and implementing dynamic migration repair on a path. S2, adopting a mixed dependency ecological system construction scheme to realize compiling, dependency and environment variable collaborative calling. S3, through deep optimization compiling of ARM architecture series instruction sets and a math library KML, the full-flow computing speed of ISCE-MintPy is effectively improved, and calculation power lossless conversion is achieved. S4, outputting matrix verification result parameters through ISCE-MintPy collaborative deployment, comparing ARM with the x86 architecture operation time, further outputting a deformation rate inversion result graph, and optimizing scientific calculation quality verification. S5, replacing server parameters, repeating the steps, and packaging, migrating and deploying ISCE-MintPy tool chain environments. The invention solves the defects existing in the background technology, and has the following beneficial effects: (1) The invention improves the compiling success rate from less than 50% to 100%. (2) The invention eliminates the virtualization overhead of Docker and the like, and the average calculation power utilization rate is close to 100 percent. (3) The invention constructs a first set of ARM architecture time sequence InSAR processing system. (4) The invention optimizes scientific calculation by optimizing ARM architecture instruction set and calling math library gain. Drawings The invention will be further described with reference to the drawings and examples. FIG. 1 is a diagram of an ARM architecture ISCE of the present invention depending on the package/library list; FIG. 2 is a diagram of an ARM architecture MintPy dependency package/library list of the present invention; FIG. 3 is a diagram of an x86 ARM architecture compile time test table of the present invention; FIG. 4 is a diagram of an ARM architecture functional verification matrix table test table of the present invention; FIG. 5 shows a chart of test tables for inversion experiments of the x86, ARM architectures ISCE2, mintPy of the present invention; FIG. 6 shows the implementation flow of ISCE's compilation on the ARM architecture of the present invention; FIG. 7 illustrates the implementation flow of MintPy compilation on the ARM architecture of the present invention; FIG. 8 is a schematic diagram of an ARM architecture math library acceleration function module of the present invention; FIG. 9 is