CN-122018981-A - MCU (micro control Unit) caching device, memory access method and electronic equipment

Abstract

The invention discloses an MCU buffer device, a memory access method and an electronic device, wherein, by adding a jump buffer, when the jump occurs, the instruction block aligned with the N bits of the address where the jump occurs is stored in the buffer, and when the jump returns, the instruction is directly read from the buffer. The invention solves the problem that the processor waits for fetching the instruction caused by cache miss when the jump returns, improves the actual execution performance of the processor, reduces the occupation of the conventional cache space and reduces the cost of the memory device of the MCU.

Inventors

• LIU XIN
• YANG ZHENWEI
• YUAN ZHIQIAO

Assignees

• 杭州朔天科技有限公司

Dates

Publication Date

20260512

Application Date

20251231

Claims (10)

1. 1. An MCU buffering device, comprising: A processor unit; A flash memory cell; and a jump buffer unit arranged between the processor unit and the flash memory unit, wherein the jump buffer unit is configured to buffer the instruction blocks aligned with the addresses where the jump occurs.
2. 2. The MCU buffering device of claim 1, wherein the skip buffer unit has a D×N bits storage structure, wherein D is depth and N is data bit width.
3. 3. The MCU buffering device of claim 2, wherein the data bit width N of the skip buffer unit is 128bits.
4. 4. The MCU buffering device of claim 1, wherein the skip buffer unit employs a last-in-first-out data replacement strategy.
5. 5. The MCU caching device according to any one of claims 1-4, wherein when jump nesting occurs, the jump buffer unit sequentially stores instruction blocks with aligned addresses where the jump occurs; upon jump back, the processor unit reads the return destination address instructions from the jump buffer unit in a last in first out order.
6. 6. The access method is characterized by comprising the following steps of: detecting a jump instruction in the execution process of the processor unit; when the function jump is detected, storing an instruction block with aligned addresses when the jump occurs into a jump buffer; When a jump return instruction is detected, directly reading a return destination address instruction from the jump buffer; And executing the return destination address instruction.
7. 7. The method of claim 6, wherein storing the block of address-aligned instructions in the jump buffer at the time of the jump comprises: judging whether the current instruction is a function jump instruction or not; If the function jumps, storing the instruction block aligned with the current address into a jump buffer, and executing the jump instruction; Otherwise, executing sequentially.
8. 8. The method of claim 6, wherein the step of reading the return destination address instruction directly from the jump buffer comprises: judging whether the current instruction is a jump return instruction or not; if the return instruction is skipped, the required return destination address instruction is read from the topmost layer of the skip buffer; if the reading is successful, executing a return destination address instruction; if the reading fails, the instruction is read from the main memory and then executed.
9. 9. The method according to claim 6, comprising: When jump nesting occurs, repeatedly executing an instruction caching process, and sequentially storing return address instructions of each layer of jump into a jump buffer; When the jump returns, the corresponding return destination address instruction is read from the jump buffer according to the last-in first-out sequence.
10. 10. An electronic device comprising a processor and a flash memory, wherein access is made between the processor and the flash memory by a method as claimed in claims 6-9.

Description

MCU (micro control Unit) caching device, memory access method and electronic equipment Technical Field The invention relates to the technical field of micro-controller units, in particular to an MCU (micro-controller unit) caching device, a memory access method and electronic equipment. Background In modern embedded systems, the performance of a microcontroller unit (MCU) depends largely on its instruction fetch efficiency. EFLASH as program memory, its access speed tends to be a bottleneck for system performance. Instruction caches and prefetch buffers are commonly employed in the prior art to improve instruction fetch efficiency. However, when jump instructions such as function calls and returns are encountered during program execution, cache misses often occur in conventional cache mechanisms. Particularly in the deep jump nest scenario, the return address instruction may have been replaced from the cache, resulting in a processor having to wait for re-fetching from main memory, resulting in reduced performance. The existing solution mainly comprises the steps of starting jump to return to target prefetching in the decoding or executing stage of a jump instruction, wherein the waiting time can be reduced, but the waiting period of FLASH still cannot be completely covered due to the late starting time of prefetching, and waiting delay is difficult to avoid. All access requests of the CPU are written into the cache, so that zero waiting of instructions during jump return is realized, but the requirement on the size of the cache is high, the cache is easy to replace when the capacity of the cache is insufficient, and the effect is limited. Therefore, an effective method is needed to solve the jump-back cache miss problem and improve the execution performance of the MCU. It should be noted that the information disclosed in the background section of the present application is only for enhancement of understanding of the general background of the present application and should not be taken as an admission or any form of suggestion that this information forms the prior art that is well known to a person skilled in the art. Disclosure of Invention In view of this, the present application provides an MCU cache device to solve the problem of instruction jump return cache miss in the prior art. In a first aspect, an embodiment of the present application provides an MCU cache device, including: A processor unit; A flash memory cell; a skip buffer unit disposed between the processor unit and the flash memory unit; The jump buffer unit is configured to buffer the instruction block with aligned addresses where the jump occurs. In combination with the first aspect of the present application, in one possible aspect, the embodiment of the present application further provides an MCU buffer device, wherein the skip buffer unit has a storage structure of d×n bits, where D is depth and N is data bit width, and in particular, the data bit width N of the skip buffer unit is 128bits. In combination with the first aspect of the present application, in one possible implementation manner, the present application further provides an MCU buffer device, where the skip buffer unit uses a last-in first-out data replacement policy. In combination with the first aspect of the present application, in one possible aspect, an embodiment of the present application further provides an MCU buffer device, where the skip buffer unit directly deletes the read data after the read data, and the subsequent data advances in sequence. In a second aspect, the present invention further provides a memory access method, including the steps of: detecting a jump instruction in the execution process of the processor unit; when the function jump is detected, storing an instruction block with aligned addresses when the jump occurs into a jump buffer; When a jump return instruction is detected, directly reading a return destination address instruction from the jump buffer; And executing the return destination address instruction. With reference to the second aspect of the present invention, in one possibility, the step of storing the instruction block aligned with the address where the jump occurs in the jump buffer includes: judging whether the current instruction is a function jump instruction or not; If the function jumps, storing the instruction block aligned with the current address into a jump buffer, and executing the jump instruction; Otherwise, executing sequentially. With reference to the second aspect of the present invention, in one possibility, the step of "reading the return destination address instruction directly from the jump buffer" includes: judging whether the current instruction is a jump return instruction or not; if the return instruction is skipped, the required return destination address instruction is read from the topmost layer of the skip buffer; if the reading is successful, executing a return destination address instruction; if the