CN-122018988-A - RISC-V vector compression method and device

CN122018988ACN 122018988 ACN122018988 ACN 122018988ACN-122018988-A

Abstract

The present disclosure relates to the field of computer technologies, and in particular, to a method and apparatus for compressing RISC-V vectors. The method comprises the steps of receiving vector compression instructions, grouping masks according to a predetermined sequence and fixed intervals according to bit widths of the masks, shifting elements in vector data to be compressed corresponding to each mask group to form intermediate compression results corresponding to the mask groups, wherein the intermediate compression results corresponding to adjacent mask groups respectively form high-level groups and low-level groups of the intermediate compression groups, and executing iterative steps of combining and compressing elements of the high-level groups and the low-level groups in each intermediate compression group in parallel to form high-level groups or low-level groups of the updated intermediate compression groups until compression of the vector data to be compressed is completed. By using the embodiment of the specification, the vector compression instruction can be executed in parallel, and the compression efficiency is improved.

Inventors

Xian Youlong

Assignees

成都群芯微电子科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260115

Claims (16)

1. A method of RISC-V vector compression, the method comprising: Receiving a vector compression instruction, wherein the vector compression instruction comprises vector data to be compressed and a mask indicating the validity of each element in the vector data to be compressed; grouping masks according to a predetermined order and fixed intervals according to bit widths of the masks; Shifting elements in vector data to be compressed corresponding to each mask packet to form an intermediate compression result corresponding to the mask packet, wherein the intermediate compression results corresponding to the adjacent mask packets respectively form a high-level group and a low-level group of the intermediate compression group; And executing the iterative steps of combining and compressing the elements of the high-order group and the low-order group in each intermediate compression group in parallel to form the high-order group or the low-order group of the updated intermediate compression group until the compression of the vector data to be compressed is completed.
2. The method of claim 1, wherein grouping masks in a predetermined order and at fixed intervals according to the bit widths of the masks further comprises: the masks of adjacent fixed intervals form one mask group in the order from low to high.
3. The method of claim 2, wherein two adjacent masks are formed into one mask packet.
4. The method of claim 1, wherein shifting a plurality of elements in vector data to be compressed for each mask packet to form an intermediate compression result for the mask packet further comprises: determining effective elements in the vector data to be compressed according to the indication of the mask in the mask packet; And sequentially shifting the effective elements in the mask packet to the low order bits of the intermediate compression result.
5. The method of claim 4, wherein shifting valid elements to low order bits of the intermediate compression result further comprises: and supplementing 0 to the high order of the intermediate compression result.
6. The method of claim 4, wherein determining valid elements in the vector data to be compressed according to the indication of the mask in the mask packet further comprises: When the mask of the mask group is 00, indicating that the corresponding two elements are invalid elements; When the mask of the mask group is 01, indicating that the corresponding first element is an invalid element and the second element is an effective element; when the mask of the mask group is 10, indicating that the corresponding first element is an effective element and the second element is an ineffective element; And when the mask of the mask group is 11, indicating that the corresponding two elements are valid elements.
7. The method of claim 4, wherein merging and compressing elements of the high-order group and the low-order group in the intermediate compression group further comprises: determining a shift bit number according to the number of invalid masks in the mask group corresponding to the low-level group in the middle compression group of the current iteration; Shifting the elements of the high-order group in the middle compression group to the right by the shift bit number to form overflow elements; and merging the overflow element with elements of a low-level group in the intermediate compression group to form an updated high-level group or low-level group of the intermediate compression group.
8. The method of claim 7, wherein merging the overflow element with elements of a low-level group in the intermediate compression group to form an updated high-level or low-level group of the intermediate compression group further comprises: And taking the overflow element and the element of the low-level group in the intermediate compression group according to bits or supplementing 0 to the high-level group in the intermediate compression group to form an updated high-level group or low-level group of the intermediate compression group.
9. The method of claim 7, wherein combining and compressing elements of the high-order groups and the low-order groups in each intermediate compression group in parallel to form the high-order or low-order groups of the updated intermediate compression group further comprises: Taking the high-level group and the low-level group of the adjacent updated intermediate compression group as the updated intermediate compression group; And executing the iteration step for the updated intermediate compression group.
10. The method of claim 1, wherein the vector data to be compressed occupies a plurality of vector registers when a vector register set multiplier LMUL is greater than 1; calculating partial compressed data of the vector data to be compressed in each vector register; taking partial compressed data of each vector register as the intermediate compression result, and taking the intermediate compression results corresponding to the two vector registers as a high-level group and a low-level group of an intermediate compression group respectively; And executing the iteration step until the compression of the vector data to be compressed is completed.
11. A RISC-V vector compression apparatus, comprising: an instruction receiving unit configured to receive a vector compression instruction, the vector compression instruction including vector data to be compressed and a mask indicating validity of each element in the vector data to be compressed; a mask grouping unit configured to group masks in a predetermined order and at fixed intervals according to bit widths of the masks; an intermediate compression group unit configured to shift elements in vector data to be compressed corresponding to each mask packet to form an intermediate compression result corresponding to the mask packet, wherein the intermediate compression results corresponding to adjacent mask packets form a high-level group and a low-level group of an intermediate compression group respectively; and the iteration unit is configured to execute the following iteration steps of combining and compressing the elements of the high-order group and the low-order group in each intermediate compression group in parallel to form the high-order group or the low-order group of the updated intermediate compression group until the compression of the vector data to be compressed is completed.
12. A vector execution unit, characterized in that it comprises means for executing the method according to any of the preceding claims 1-10.
13. A processor comprising the vector execution unit of claim 12.
14. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor is the processor of claim 13.
15. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the method of any of the preceding claims 1-10.
16. A computer program product, characterized in that the computer program product comprises a computer program which, when executed by a processor, implements the method of any one of claims 1-10.

Description

RISC-V vector compression method and device Technical Field The present disclosure relates to the field of computer technologies, and in particular, to a method and apparatus for compressing RISC-V vectors. Background RISC-V is an abbreviation for the fifth generation of reduced instruction set, a reduced instruction set that is currently in wider use. The RISC-V vector instruction set proposes a variable length vector instruction set. The arithmetic instructions of the RISC-V vector instruction set have a feature that, for binary operation, the nth element of one vector will only operate with the nth element of the other vector. Vector compression instructions in RISC-V architecture enable efficient compression of vector data. However, in the prior art, a traversal method is used to sequentially stack valid source elements at the lowest element positions of the destination registers by sequentially determining whether the source operands are valid or not at the lowest element positions. The problem with the traversal method is that the timing is poor and the execution period required is long. How to control data operation in the cache to reduce the frequent eviction and backfilling of cache lines with the same address, so as to reduce the system power consumption is a problem to be solved. Disclosure of Invention In order to solve the problems in the prior art, the embodiment of the specification provides a RISC-V vector compression method and device, which solve the problem of low vector data compression efficiency in the prior art. The embodiment of the specification provides a RISC-V vector compression method, which comprises the following steps: Receiving a vector compression instruction, wherein the vector compression instruction comprises vector data to be compressed and a mask indicating the validity of each element in the vector data to be compressed; grouping masks according to a predetermined order and fixed intervals according to bit widths of the masks; Shifting elements in vector data to be compressed corresponding to each mask packet to form an intermediate compression result corresponding to the mask packet, wherein the intermediate compression results corresponding to the adjacent mask packets respectively form a high-level group and a low-level group of the intermediate compression group; And executing the iterative steps of combining and compressing the elements of the high-order group and the low-order group in each intermediate compression group in parallel to form the high-order group or the low-order group of the updated intermediate compression group until the compression of the vector data to be compressed is completed. As a further aspect of the present specification, grouping the masks according to the bit widths of the masks in a predetermined order and at fixed intervals further includes: the masks of adjacent fixed intervals form one mask group in the order from low to high. As a further aspect of the present description, two adjacent masks are formed into one mask group. As still a further aspect of the present specification, shifting a plurality of elements in vector data to be compressed corresponding to each mask packet, forming an intermediate compression result corresponding to the mask packet further includes: determining effective elements in the vector data to be compressed according to the indication of the mask in the mask packet; And sequentially shifting the effective elements in the mask packet to the low order bits of the intermediate compression result. As another further aspect of the present specification, shifting the valid element to a lower order of the intermediate compression result further includes: and supplementing 0 to the high order of the intermediate compression result. As another further aspect of the present specification, determining valid elements in the vector data to be compressed according to the indication of the mask in the mask packet further includes: When the mask of the mask group is 00, indicating that the corresponding two elements are invalid elements; When the mask of the mask group is 01, indicating that the corresponding first element is an invalid element and the second element is an effective element; when the mask of the mask group is 10, indicating that the corresponding first element is an effective element and the second element is an ineffective element; And when the mask of the mask group is 11, indicating that the corresponding two elements are valid elements. As another further aspect of the present specification, the merging and compressing the elements of the high-order group and the low-order group in the intermediate compression group further includes: determining a shift bit number according to the number of invalid masks in the mask group corresponding to the low-level group in the middle compression group of the current iteration; Shifting the elements of the high-order group in the middle compression group to th