CN-122018989-A - Processor, chip, electronic device and instruction processing method

CN122018989ACN 122018989 ACN122018989 ACN 122018989ACN-122018989-A

Abstract

The embodiment of the disclosure provides a processor, a chip, electronic equipment and an instruction processing method, and belongs to the technical field of chips. The processor comprises an instruction processing unit and a stack, wherein the instruction processing unit is used for generating current instruction execution information and storing the current instruction execution information to the stack in the current instruction execution process, the current instruction execution information comprises address information of a next instruction to be executed, address information of a convergence point instruction and recursion depth information, the recursion depth information represents a difference value between the executed times of a function calling instruction and the executed times of a return instruction, the instruction execution information is read from the stack after the current instruction is executed, if the fact that the address of the next instruction to be executed is the same as the address of the convergence point instruction and the difference value is 0 is determined, stack-stripping operation is carried out on the stack, and the operation of reading the instruction execution information from the stack is returned until the stack is empty. The method and the device can avoid the problem of calculation errors of the thread program counter in the recursive function nesting scene.

Inventors

ZHOU JUN
CHEN WEILUN
HUANG LANZHIGUAN
LIU XINHONG
WANG JIAN

Assignees

北京有竹居网络技术有限公司

Dates

Publication Date: 20260512
Application Date: 20241111

Claims (14)

1. A processor includes an instruction processing unit and a stack; the instruction processing unit is used for: generating current instruction execution information and storing the current instruction execution information to the stack in the current instruction execution process, wherein the current instruction execution information comprises address information of a next instruction to be executed, address information of a convergence point instruction and recursion depth information; And if the address of the next instruction to be executed is determined to be the same as the address of the converging point instruction based on the read instruction execution information and the difference value is 0, executing a stack-stripping operation on the stack, and returning the operation of reading the instruction execution information from the stack until the stack is empty.
2. The processor of claim 1, wherein the recursive depth information is presented in the form of recursive depth values; If the current instruction is a function call instruction, determining the sum of the recursion depth value in the previous instruction execution information and the first preset value as the recursion depth value in the current instruction execution information; if the current instruction is a function return instruction, determining the difference between the recursion depth value in the previous instruction execution information and the first preset value as the recursion depth value in the current instruction execution information; the previous instruction execution information is instruction execution information generated in the previous instruction execution process before the current instruction is executed; The storing the current instruction execution information to the stack includes: and updating the stack top element of the stack by adopting the current instruction execution information.
3. The processor of claim 2, wherein if the current instruction is a branch jump instruction, setting a recursion depth value in the generated current instruction execution information to a second preset value; The storing the current instruction execution information to the stack includes: pushing the current instruction execution information to the stack; If the address of the next instruction to be executed is determined to be the same as the address of the convergence point instruction based on the read instruction execution information and the difference value is 0, performing a pop operation on a stack top element in the stack, including: And if the address of the next instruction to be executed is determined to be the same as the address of the convergence point instruction based on the read instruction execution information, and the recursion depth value is equal to the second preset value, executing a pop operation on a stack top element in the stack.
4. A processor according to claim 3, wherein the first preset value is 1 and the second preset value is 0.
5. The processor of claim 1, wherein the recursive depth information comprises a function call number value and a return number value, wherein the function call number value characterizes a number of times a function call instruction has been executed; If the current instruction is a function call instruction, determining the sum of a function call sub-value in the previous instruction execution information and a third preset [ P-137014-CN-PRI-1] [ HS2410896CCN ] value as the function call sub-value in the current instruction execution information; And determining the sum of the return sub-value in the previous instruction execution information and the third preset value as the return sub-value in the current instruction execution information.
6. The processor of claim 5, wherein the third preset value is 1.
7. The processor of any of claims 1-6, wherein the processor is further configured to: And if the instruction address of the next instruction to be executed is different from the address of the convergence point instruction based on the read instruction execution information, and/or the difference value is not 0, taking the next instruction to be executed as an updated current instruction, returning to the step of generating the current instruction execution information and storing the current instruction execution information to the stack in the current instruction execution process until the stack is empty.
8. A chip comprising a processor as claimed in any one of claims 1 to 7.
9. An electronic device comprising a processor as claimed in any one of claims 1-7, or a chip as claimed in claim 8.
10. An instruction processing method applied to a processor including an instruction processing unit and a stack, the method comprising: generating current instruction execution information and storing the current instruction execution information to the stack in the current instruction execution process by the instruction processing unit, wherein the current instruction execution information comprises instruction address information of a next instruction to be executed, address information of a convergence point instruction and recursion depth information; And if the address of the next instruction to be executed is determined to be the same as the address of the converging point instruction based on the read instruction execution information and the difference value is 0, executing a stack stripping operation on the stack, and returning the operation of reading the instruction execution information from the stack until the stack is empty.
11. The method of claim 10, wherein the recursive depth information is presented in the form of recursive depth values; If the current instruction is a function call instruction, determining the sum of the recursion depth value in the previous instruction execution information and the first preset value as the recursion depth value in the current instruction execution information; if the current instruction is a function return instruction, determining the difference between the recursion depth value in the previous instruction execution information and the first preset value as the recursion depth value in the current instruction execution information; the previous instruction execution information is instruction execution information generated in the previous instruction execution process before the current instruction is executed; The storing the current instruction execution information to the stack includes: and updating the stack top element of the stack by adopting the current instruction execution information.
12. The method according to claim 11, wherein if the current instruction is a branch jump instruction, setting a recursion depth value in the generated current instruction execution information to a second preset value; [ P-137014-CN-PRI-1] [ HS2410896CCN ] said storing said current instruction execution information to said stack, comprising: pushing the current instruction execution information to the stack; If the address of the next instruction to be executed is determined to be the same as the address of the convergence point instruction based on the read instruction execution information and the difference value is 0, performing a pop operation on a stack top element in the stack, including: And if the address of the next instruction to be executed is determined to be the same as the address of the convergence point instruction based on the read instruction execution information, and the recursion depth value is equal to the second preset value, executing a pop operation on a stack top element in the stack.
13. The method of claim 10, wherein the recursive depth information comprises a function call number value and a return number value, wherein the function call number value characterizes a number of times a function call instruction has been executed; If the current instruction is a function call instruction, determining the sum of a function call sub-value in the previous instruction execution information and a third preset value as the function call sub-value in the current instruction execution information; And determining the sum of the return sub-value in the previous instruction execution information and the third preset value as the function call sub-value in the current instruction execution information.
14. The method of any of claims 10-13, wherein the method further comprises: If it is determined that the instruction address of the next instruction to be executed is different from the address of the converging point instruction based on the read instruction execution information, and/or if it is determined that the difference is not 0, the instruction processing unit is configured to take the next instruction to be executed as an updated current instruction, return the current instruction to the current instruction execution process, generate current instruction execution information, and store the current instruction execution information to the stack until the stack is empty.

Description

Processor, chip, electronic device and instruction processing method Technical Field The embodiment of the disclosure relates to the technical field of chips, in particular to a processor, a chip, electronic equipment and an instruction processing method. Background To improve computing performance, SIMT (Single Instruction Multi Thread, single instruction stream multithreading) architecture may be employed in processors that support parallel processing. SIMT refers to binding multiple threads together to lock-step execution of instruction stream operations. During instruction execution, different threads may enter different instruction branches within a conditional branch. For example, when a conditional branch instruction is encountered, the execution results of some threads in the thread bundle satisfy the condition indicated by the branch instruction, while the execution results of other threads do not satisfy the condition, the threads satisfying the condition will branch to execute a first branch, while the other threads execute a second branch different from the first branch. In order to reduce the communication cost between the compiler and the processor and improve the instruction processing efficiency, stacks corresponding to SIMT, SIMT_Stack, are usually arranged in the processor and are used for storing the execution context and temporary data in the thread execution process so as to assist the processor to complete the instruction processing process. In the above instruction processing process based on SIMT_Stack, once a thread executes to a convergence point, that is, when the next instruction to be executed by the thread is the same as an instruction at the convergence point (hereinafter abbreviated as a convergence point instruction), a pop operation is performed on the thread-related data stored in the Stack so as to cause each thread to converge, and then the instruction at the convergence point position is executed in parallel. By adopting the instruction processing mode, the program counter of the thread is caused to calculate errors under the scene of recursive function nesting. Disclosure of Invention In view of the above, embodiments of the present disclosure provide a processor, a chip, an electronic device, and an instruction processing method, so as to at least solve or alleviate the above-mentioned problems. According to a first aspect of embodiments of the present disclosure, there is provided a processor comprising an instruction processing unit and a stack; The instruction processing unit is used for generating current instruction execution information and storing the current instruction execution information into the stack in the current instruction execution process, wherein the current instruction execution information comprises address information of a next instruction to be executed, address information of a converging instruction and recursive depth information, the recursive depth information characterizes a difference value between the executed times of a function calling instruction and the executed times of a function returning instruction, after the current instruction execution is finished, the instruction execution information is read from the stack, and if the address of the next instruction to be executed is determined to be the same as the address of the converging instruction based on the read instruction execution information and the difference value is 0, a stack-stripping operation is executed on the stack, and the operation of reading the instruction execution information from the stack is returned until the stack is empty. According to a second aspect of embodiments of the present disclosure, there is provided a chip comprising a processor as described in the first aspect. According to a third aspect of embodiments of the present disclosure, there is provided an electronic device, including a processor as described in the first aspect, or a chip as described in the second aspect. According to a fourth aspect of embodiments of the present disclosure, there is provided an instruction processing method applied to a processor including an instruction processing unit and a stack, the method comprising: the method comprises the steps of generating current instruction execution information in the current instruction execution process and storing the current instruction execution information into a stack through an instruction processing unit, wherein the current instruction execution information comprises instruction address information of a next instruction to be executed, address information of a converging instruction and recursion depth information, the recursion depth information represents a difference value between the executed times of a function calling instruction and the executed times of a function returning instruction, the instruction processing unit reads the instruction execution information from the stack after the current instruction is executed