CN-122018990-A - Branch prediction processing architecture, branch prediction method, chip and equipment

Abstract

The application relates to the technical field of branch prediction of a processor and provides a branch prediction processing architecture, a branch prediction method, a chip and equipment, wherein the architecture comprises a branch information buffer area, a branch information processing module and a branch information processing module, wherein the branch information buffer area is used for storing a plurality of entries, at least one entry is an expansion entry, and the expansion entry comprises branch information of a first prediction block and branch information of at least one second prediction block related to the execution sequence of the first prediction block; the branch prediction system comprises a branch predictor for generating branch direction prediction information for a branch instruction in a first prediction block and a branch instruction in a second prediction block in parallel based on branch information acquired from an extension entry in a single branch prediction operation, and a prediction logic unit for generating branch prediction results of the first prediction block and the second prediction block according to the branch direction prediction information and address information in the branch information. The embodiment of the application can improve the single-period prediction bandwidth of the branch predictor on the premise of not obviously increasing hardware overhead and time sequence pressure.

Inventors

• PAN YINGXI
• HU SHIWEN

Assignees

• 成都群芯微电子科技有限公司

Dates

Publication Date

20260512

Application Date

20251216

Claims (20)

1. 1. A branch prediction processing architecture, comprising: A branch information buffer for storing a plurality of entries, wherein at least one entry is an extended entry, the extended entry containing branch information of a first prediction block and branch information of at least one second prediction block related to an order of execution of the first prediction block; A branch predictor for generating branch direction prediction information for the branch instruction in the first prediction block and the branch instruction in the second prediction block in parallel based on the branch information acquired from the extension entry in a single branch prediction operation; And the prediction logic unit is used for generating branch prediction results of the first prediction block and the second prediction block according to the branch direction prediction information and the address information in the branch information.
2. 2. The branch prediction processing architecture of claim 1, wherein the extension entry comprises: the location, type and jump target address of branch instructions in said first prediction block, and The location, type and jump target address of branch instructions within the second prediction block.
3. 3. The branch prediction processing architecture of claim 1, wherein the branch information buffer comprises a branch target cache.
4. 4. The branch prediction processing architecture of claim 1, wherein the branch predictor comprises a global history-based branch predictor.
5. 5. The branch prediction processing architecture of claim 4, wherein the number of second prediction blocks is one; the branch predictor based on the global history is a tagged geometric history length branch predictor TAGE; The generating branch direction prediction information for the branch instruction in the first prediction block and the branch instruction in the second prediction block in parallel based on the branch information acquired from the extension entry in the single branch prediction operation includes: In a single query operation, context information for distinguishing prediction blocks to which the branch instruction belongs is combined with a program counter value and global history information to form an index, and TAGE entries of the corresponding branch instructions in the first prediction block and the second prediction block are respectively queried from a plurality of prediction tables of the TAGE according to the index.
6. 6. The branch prediction processing architecture as recited in claim 5, wherein said context information is a prediction block identification, said program counter value, and said global history information forming input parameters for a hash function of a tag entry tag of said tag.
7. 7. The branch prediction processing architecture of claim 6, wherein the prediction block identification is one bit wide.
8. 8. The branch prediction processing architecture of claim 5, wherein the context information is an identification field contained in a tag entry of the tag.
9. 9. The branch prediction processing architecture of claim 5, wherein said generating branch prediction results for said first prediction block and said second prediction block based on said branch direction prediction information and address information in said branch information comprises: when a branch instruction corresponding to a current program counter value in the first prediction block meets a first condition, determining an end address of the first prediction block as the current program counter value plus the length of the first prediction block, generating only a branch prediction result of the first prediction block, and determining branch information of the second prediction block as invalid information, wherein the first condition comprises that the branch instruction is a conditional branch and the branch direction is non-jump; when a branch instruction corresponding to the current program counter value in the first prediction block meets a second condition, determining a jump target address of the first prediction block to determine a start address of the second prediction block, wherein the second condition comprises that the branch instruction is an unconditional branch or the branch instruction is a conditional branch and the branch direction is jump; When a branch instruction corresponding to the current program counter value in the second prediction block meets a second condition under the condition that the branch instruction corresponding to the current program counter value in the first prediction block meets the second condition, determining an ending address of the second prediction block as a starting address of the second prediction block plus an offset of the second prediction block, and generating a branch prediction result of the first prediction block and a branch prediction result of the second prediction block; when a branch instruction corresponding to the current program counter value in the second prediction block meets the first condition under the condition that the branch instruction corresponding to the current program counter value in the first prediction block meets the second condition, determining the ending address of the second prediction block as the starting address of the second prediction block plus the length of the second prediction block, and generating a branch prediction result of the first prediction block and a branch prediction result of the second prediction block; The branch prediction result comprises a starting address, an ending address, a jump identifier and a jump target address of a corresponding prediction block.
10. 10. The branch prediction processing architecture as recited in claim 5, wherein the branch prediction processing architecture further comprises: and the updating logic unit is used for updating the expansion entry of the branch information buffer area and the TAGE entry of the TAGE.
11. 11. The branch prediction processing architecture of claim 10, wherein said updating the extended entry of the branch information buffer comprises: And for the first prediction block and the second prediction block which have completed the instruction fetching or execution of the branch instruction, when the branch instruction meets a preset condition, updating the branch information of the branch instruction in the second prediction block into an expansion entry corresponding to the first prediction block.
12. 12. The branch prediction processing architecture of claim 11, wherein the predetermined condition comprises: The branch instruction of the first prediction block is not an indirect branch instruction; no more than one conditional branch instruction contained in the second prediction block, and The branch instruction in the second prediction block is not an indirect jump instruction outside of the return class.
13. 13. The branch prediction processing architecture of claim 10, wherein the updating of the tag entry of the tag comprises: Updating the TAGE entry corresponding to the branch instruction in the first prediction block, and updating the TAGE entry corresponding to the branch instruction in the second prediction block when the expansion entry of the branch instruction is stored in the first prediction block.
14. 14. The branch prediction processing architecture of claim 13, wherein said updating a tag entry of said tag further comprises: And when the branch predictor does not have the idle TAGE entries, replacing TAGE entries which correspond to the branch instructions in the second prediction block and meet the specified conditions, wherein the specified conditions are the minimum useful value and/or the minimum saturation counter value.
15. 15. A method of branch prediction, comprising: The method comprises the steps of obtaining branch information from an extension item of a branch information buffer, wherein the extension item comprises branch information of a first prediction block and branch information of at least one second prediction block related to the execution sequence of the first prediction block; Causing a branch predictor to perform a single branch prediction operation based on the acquired branch information to generate branch direction prediction information for the branch instruction in the first prediction block and the branch instruction in the second prediction block in parallel; and enabling a prediction logic unit to generate branch prediction results of the first prediction block and the second prediction block according to the branch direction prediction information and the address information in the branch information.
16. 16. The branch prediction method as set forth in claim 15, wherein the number of second prediction blocks is one, the branch predictor is a global history-based direction predictor, and the global history-based direction predictor comprises a tagged geometric history length branch predictor TAGE.
17. 17. The branch prediction method of claim 16, wherein the performing a single branch prediction operation based on the obtained branch information to generate branch direction prediction information for the branch instruction in the first prediction block and the branch instruction in the second prediction block in parallel comprises: In a single branch prediction operation executed based on the acquired branch information, combining context information for distinguishing prediction blocks to which the branch instruction belongs with a program counter value and global history information to form an index, and respectively inquiring TAGE entries of corresponding branch instructions in the first prediction block and the second prediction block from a plurality of prediction tables of the TAGE according to the index.
18. 18. The branch prediction method as claimed in claim 16, wherein said generating branch prediction results of said first prediction block and said second prediction block based on said branch direction prediction information and address information in said branch information, comprises: when a branch instruction corresponding to a current program counter value in the first prediction block meets a first condition, determining an end address of the first prediction block as the current program counter value plus the length of the first prediction block, generating only a branch prediction result of the first prediction block, and determining branch information of the second prediction block as invalid information, wherein the first condition comprises that the branch instruction is a conditional branch and the branch direction is non-jump; when a branch instruction corresponding to the current program counter value in the first prediction block meets a second condition, determining a jump target address of the first prediction block to determine a start address of the second prediction block, wherein the second condition comprises that the branch instruction is an unconditional branch or the branch instruction is a conditional branch and the branch direction is jump; When a branch instruction corresponding to the current program counter value in the second prediction block meets a second condition under the condition that the branch instruction corresponding to the current program counter value in the first prediction block meets the second condition, determining an ending address of the second prediction block as a starting address of the second prediction block plus an offset of the second prediction block, and generating a branch prediction result of the first prediction block and a branch prediction result of the second prediction block; when a branch instruction corresponding to the current program counter value in the second prediction block meets the first condition under the condition that the branch instruction corresponding to the current program counter value in the first prediction block meets the second condition, determining the ending address of the second prediction block as the starting address of the second prediction block plus the length of the second prediction block, and generating a branch prediction result of the first prediction block and a branch prediction result of the second prediction block; The branch prediction result comprises a starting address, an ending address, a jump identifier and a jump target address of a corresponding prediction block.
19. 19. The branch prediction method of claim 16, wherein the branch prediction method further comprises: and enabling an updating logic unit to update the expansion entry of the branch information buffer and the TAGE entry of the TAGE.
20. 20. The branch prediction method of claim 19, wherein said updating the extended entry of the branch information buffer comprises: And for the first prediction block and the second prediction block which have completed the instruction fetching or execution of the branch instruction, when the branch instruction meets a preset condition, updating the branch information of the branch instruction in the second prediction block into an expansion entry corresponding to the first prediction block.

Description

Branch prediction processing architecture, branch prediction method, chip and equipment Technical Field The present application relates to the field of branch prediction technologies of processors, and in particular, to a branch prediction processing architecture, a branch prediction method, a chip, and a device. Background Branch prediction Branch Prediction refers to predicting which branch will be executed before the end of execution of a branch instruction in order to provide for the next branch to be executed in advance, thereby improving the performance of the instruction pipeline of the processor. In modern high performance processors, the performance of the branch predictor is critical, which directly affects the efficiency of the instruction pipeline. With the increasing width of the finger of the processor, the requirement for bandwidth of the branch predictor is also increasing. Multi-step branch predictors have been developed that aim to produce multiple consecutive prediction blocks (prediction blocks) within a single prediction period to improve prediction throughput. However, conventional multi-step branch predictor schemes have significant limitations. For example, in one known embodiment, a predictor correlates information of neighboring prediction blocks by expanding entry contents of a branch target cache (Branch Target Buffer, BTB) to generate two prediction blocks in a single prediction. But this scheme typically severely limits the second prediction block from containing conditional branch instructions or requires additional serial prediction queries to be made on it when processing it. This is because high-precision direction prediction of conditional branches is heavily dependent on complex predictors, such as tagged geometry length branch predictors (Tagged Geometric History Length Branch Predictor, tag), and multiple serial queries to such predictors can significantly increase critical path delay, create timing problems, and make it difficult to meet the frequency requirements of high performance processors. Another known multi-step branching scheme attempts to stitch multiple prediction blocks within a fixed prediction window, and if the prediction block jumps out of the prediction window, multi-step prediction cannot continue. Therefore, the multi-step branch predictor in the prior art has difficulty in efficiently supporting the situation that a continuous plurality of prediction blocks generated in one prediction may each include a conditional branch while maintaining a high clock frequency and low hardware overhead. This limits further increases in branch predictor bandwidth, a critical issue that limits processor front-end performance. Disclosure of Invention The embodiment of the application aims to provide a branch prediction processing architecture, a branch prediction method, a chip and equipment, so as to improve the single-cycle prediction bandwidth of a branch predictor on the premise of not obviously increasing hardware overhead and time sequence pressure. To achieve the above object, in one aspect, an embodiment of the present application provides a branch prediction processing architecture, including: A branch information buffer for storing a plurality of entries, wherein at least one entry is an extended entry, the extended entry containing branch information of a first prediction block and branch information of at least one second prediction block related to an order of execution of the first prediction block; A branch predictor for generating branch direction prediction information for the branch instruction in the first prediction block and the branch instruction in the second prediction block in parallel based on the branch information acquired from the extension entry in a single branch prediction operation; And the prediction logic unit is used for generating branch prediction results of the first prediction block and the second prediction block according to the branch direction prediction information and the address information in the branch information. In the branch prediction processing architecture of the embodiment of the present application, the extension entry includes: the location, type and jump target address of branch instructions in said first prediction block, and The location, type and jump target address of branch instructions within the second prediction block. In the branch prediction processing architecture of the embodiment of the present application, the branch information buffer includes a branch target cache. In the branch prediction processing architecture of the embodiment of the application, the branch predictor comprises a branch predictor based on global history. In the branch prediction processing architecture of the embodiment of the application, the number of the second prediction blocks is one, and the branch predictor based on the global history is a tagged geometric history length branch predictor TAGE; The generating branch