CN-122018994-A - RISC-V branch predictor closed loop verification method and system

CN122018994ACN 122018994 ACN122018994 ACN 122018994ACN-122018994-A

Abstract

The application relates to the technical field of processor verification, and provides a closed loop verification method and system of a RISC-V branch predictor, comprising the steps of providing a plurality of test modes facing to a branch predictor micro-architecture, wherein each test mode corresponds to a branch behavior characteristic and has parameterized configuration; the method comprises the steps of receiving a random seed, selecting a target test mode from a plurality of test modes based on the random seed, determining parameters for the target test mode, and generating a corresponding RISC-V assembly test program according to the target test mode and the parameters thereof so as to carry out closed loop verification on a RISC-V branch predictor. According to the application, through the parameterized test mode and the random seed driving mechanism facing the micro-architecture, the efficient closed-loop verification is realized, the problem that the test excitation randomness is too high or the simulation time is too long in the prior art is solved, and the verification efficiency is effectively improved.

Inventors

JIAO FANG
WANG XINYU
ZHU DANQING
XU YIWEI
WANG YAN
GUO YIFAN
YANG MINCONG

Assignees

翼华科技(北京)股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260409

Claims (10)

1. A method for closed loop verification of a RISC-V branch predictor, the method comprising: providing a plurality of test modes facing to a branch predictor micro-architecture, wherein each test mode corresponds to a branch behavior characteristic and has parameterized configuration; Receiving a random seed, selecting a target test mode from a plurality of test modes based on the random seed, and determining parameters for the target test mode; And generating a corresponding RISC-V assembly test program according to the target test mode and parameters thereof so as to carry out closed loop verification on the RISC-V branch predictor.
2. The method of claim 1, wherein the plurality of test patterns comprises: the first type of test mode is a pressure test mode designed for a branch predictor micro-architecture submodule; The second type of test pattern is a predictive rate benchmark pattern for reproducing typical branch behavior characteristics in standard benchmark test procedures.
3. The method of claim 2, wherein the microarchitectural submodule for which the pressure test mode is directed includes at least one of a branch target buffer BTB, a branch history table BHT, a return address stack RAS, an indirect branch target buffer iBTB, and a pipeline, wherein each pressure test mode corresponds to a particular microarchitectural behavior including at least one of BTB capacity overflow, BHT saturation counter hysteresis, RAS depth overflow, iBTB multi-state skip; Typical branch behavior characteristics reproduced by the prediction rate reference mode are derived from Dhrystone, coreMark or SPEC CPU standard reference test programs; the prediction rate reference mode comprises at least one of a re-circulation mode, a bias if-else mode, a nested circulation mode, a related branch pair mode, a call return mode, a periodic mode, a phase change branch mode and a phase change branch mode, wherein the re-circulation mode is used for simulating a high bias circulation branch, the bias if-else mode is used for simulating a data dependent conditional branch, the nested circulation mode is used for simulating a multi-layer circulation structure in matrix operation, the related branch pair mode is used for constructing a branch sequence with global historical correlation, the call return mode is used for testing a return address stack, the periodic mode is used for testing historical pattern matching, and the phase change branch mode is used for testing adaptation speed of a predictor for changing the behavior of the branch.
4. The method of claim 1, wherein generating the corresponding RISC-V assembly test program based on the target test pattern and its parameters comprises: Synchronously generating branch execution tracks consistent with the RISC-V assembly test program logic while generating the RISC-V assembly test program based on the random seed; Inputting the branch execution track into a plurality of preset branch predictor software models for simulation analysis, outputting theoretical prediction rate data corresponding to each model, and forming an ideal prediction rate report associated with the assembly test program.
5. The method of claim 4, wherein the plurality of pre-set branch predictor software models comprises a plurality of models having a stepwise distribution of complexity, wherein the branch predictor software models comprise Bimodal predictor models, gshare predictor models, tournament predictor models, TAGE predictor models, or TAGE-lite predictor models.
6. The method as recited in claim 4, further comprising: running the RISC-V assembly test program in an RTL simulation environment to obtain an actual branch misprediction rate; And comparing the actual branch misprediction rate with theoretical prediction rate data in the ideal prediction rate report, and judging whether the branch predictor design meets the performance requirement or not according to a comparison result.
7. The method of claim 2, wherein selecting a target test pattern from a plurality of the test patterns based on the random seed further comprises: selecting a test mode from the corresponding test mode set according to the received operation mode parameters; The operation mode includes: stress mode is selected from the first type of test mode only; predict modes, which are selected from the second type of test modes only; and selecting a mixed mode from the combined set of the first type of test mode and the second type of test mode.
8. The method of claim 7, wherein the mixed mode comprises randomly inserting a pressure test pattern between prediction rate reference patterns to generate a hybrid test sequence for testing the branch predictor's ability to recover after being subjected to extreme microarchitectural pressure.
9. The method of claim 1, wherein the test pattern sequence and the parameter configuration generated under the same random seed input are completely consistent in the process of selecting the target test pattern from the plurality of test patterns based on the random seed, so as to ensure the repeatability of the verification result.
10. A RISC-V branch predictor closed loop verification system, the system comprising: a pattern library for providing a plurality of test patterns for the branch predictor microarchitecture, each test mode corresponds to a branch behavior feature and has parameterized configuration; the receiving module is used for receiving a random seed, selecting a target test mode from a plurality of test modes based on the random seed, and determining parameters for the target test mode; And the generating module is used for generating a corresponding RISC-V assembly test program according to the target test mode and the parameters thereof so as to carry out closed loop verification on the RISC-V branch predictor.

Description

RISC-V branch predictor closed loop verification method and system Technical Field The application relates to the technical field of chips, in particular to a closed loop verification method and system for a RISC-V branch predictor. Background Currently, in the field of processor chip design, the performance of a branch predictor directly affects the execution efficiency of a processor. The existing processor branch predictor verification technology mainly comprises a performance evaluation method based on a benchmark test program, a manually written directional assembly test method, a random instruction generator and the like. Although the method based on SPECint2017 standard benchmark test procedures can reflect the real load, the instruction number is as high as billions to billions, and the operation in the RTL simulation stage takes weeks to months, so that the performance evaluation is forced to be deferred to the FPGA prototype or the post-flow stage, which is time-consuming and has extremely high repair cost when the performance defect is found in the later development stage. The branch mode generated by the general random instruction generator is too random, lacks bias characteristics and historical correlation in a real workload, cannot effectively distinguish performance differences of predictors with different complexity, and is difficult to systematically cover micro-architecture boundary conditions such as overflow of the capacity of a branch target buffer, deep overflow of a return address stack and the like. In addition, stimulus generation is separated from a prediction rate baseline in the existing verification process, and the lack of a reference for the "prediction rate" leads to the difficulty that engineers cannot distinguish between the design defect of the predictor and the test stimulus itself, and the "left shift" of the verification process is difficult to realize. Therefore, there is an urgent need for a method and system that can quickly and efficiently evaluate branch predictor performance and implement closed loop verification at an early stage of chip development. Disclosure of Invention An objective of the embodiments of the present application is to provide a closed loop verification method and system for RISC-V branch predictor, which are used for solving the above technical problems. In a first aspect, the present application provides a method for closed loop verification of a RISC-V branch predictor, the method comprising: providing a plurality of test modes facing to a branch predictor micro-architecture, wherein each test mode corresponds to a branch behavior characteristic and has parameterized configuration; Receiving a random seed, selecting a target test mode from a plurality of test modes based on the random seed, and determining parameters for the target test mode; And generating a corresponding RISC-V assembly test program according to the target test mode and parameters thereof so as to carry out closed loop verification on the RISC-V branch predictor. In an alternative embodiment, the plurality of test patterns includes: the first type of test mode is a pressure test mode designed for a branch predictor micro-architecture submodule; The second type of test pattern is a predictive rate benchmark pattern for reproducing typical branch behavior characteristics in standard benchmark test procedures. In an alternative embodiment, the micro-architecture sub-modules for which the pressure test mode is directed include at least one of a branch target buffer BTB, a branch history table BHT, a return address stack RAS, an indirect branch target buffer iBTB, and a pipeline, each pressure test mode corresponds to a particular micro-architecture behavior including at least one of BTB capacity overflow, BHT saturation counter hysteresis, RAS depth overflow, iBTB multi-state skip; Typical branch behavior characteristics reproduced by the prediction rate reference mode are derived from Dhrystone, coreMark or SPEC CPU standard reference test programs; the prediction rate reference mode comprises at least one of a re-circulation mode, a bias if-else mode, a nested circulation mode, a related branch pair mode, a call return mode, a periodic mode, a phase change branch mode and a phase change branch mode, wherein the re-circulation mode is used for simulating a high bias circulation branch, the bias if-else mode is used for simulating a data dependent conditional branch, the nested circulation mode is used for simulating a multi-layer circulation structure in matrix operation, the related branch pair mode is used for constructing a branch sequence with global historical correlation, the call return mode is used for testing a return address stack, the periodic mode is used for testing historical pattern matching, and the phase change branch mode is used for testing adaptation speed of a predictor for changing the behavior of the branch. In an alternative embodiment, the generating