CN-122018997-A - Re-execution method, device and equipment of access instruction and storage medium

Abstract

The application provides a re-execution method, device and equipment of a memory access instruction and a storage medium, wherein the method applied to a processor comprises the steps of determining that a re-execution event of the memory access instruction occurs, determining a target feedback port from at least one preset feedback port based on the re-execution event or a target pipeline level of the memory access instruction, and sending a retransmission request to a reservation station through the target feedback port so that the reservation station retransmits the memory access instruction based on the retransmission request. By the technical scheme, the execution efficiency of the memory access instruction can be improved, so that the execution efficiency of the processor is further improved.

Inventors

• Huan Dandan
• LI ZUSONG
• YANG YE

Assignees

• 北京微核芯科技有限公司

Dates

Publication Date

20260512

Application Date

20260414

Claims (16)

1. 1. A method of re-executing a memory access instruction, the method being applied to a processor, the method comprising: determining a re-execution event of a memory access instruction, and determining a target feedback port from at least one preset feedback port based on the re-execution event or a target pipeline level of the memory access instruction; and sending a retransmission request to a reservation station through the target feedback port so that the reservation station retransmits the access instruction based on the retransmission request.
2. 2. The method of claim 1, wherein each feedback port corresponds to at least one pipeline stage, different pipeline stages corresponding to different feedback ports differ, and determining a target feedback port from a plurality of preset feedback ports based on a target pipeline stage in which the memory access instruction is located comprises: and taking the feedback port corresponding to the target pipeline stage as the target feedback port.
3. 3. The method according to claim 2, wherein the access instruction is an fetch instruction, the fetch pipeline corresponding to the fetch instruction includes four pipeline stages, the feedback port includes a fast feedback port and a slow feedback port, the fast feedback port is disposed at a pipeline stage 1 of the fetch pipeline, the slow feedback port is disposed at a pipeline stage 3 of the fetch pipeline, and the taking the feedback port corresponding to the target pipeline stage as the target feedback port includes: determining the target pipeline stage as the pipeline stage 0 or the pipeline stage 1 of the fetch pipeline, taking the quick feedback port as the target feedback port, or And determining the target pipeline stage as the pipeline stage 2 or the pipeline stage 3 of the fetch pipeline, and taking the slow feedback port as the target feedback port.
4. 4. The method of claim 2, wherein the memory access instruction is a memory access instruction, the memory access pipeline corresponding to the memory access instruction includes four pipeline stages, the feedback port includes a memory access retransmission feedback port, the memory access retransmission feedback port is set in the pipeline stage 1, and the determining the target feedback port from a plurality of preset feedback ports based on the target pipeline stage in which the memory access instruction is located includes: And determining the target pipeline stage as the pipeline stage 0 or the pipeline stage 1 of the stock pipeline, and taking the stock retransmission feedback port as the target feedback port.
5. 5. The method of claim 1, wherein the re-execution event comprises at least one of: a translation look-aside buffer failure; Data cache bank access conflicts; The data cache access failure queue is full; when the deposit instruction corresponding to the fetch instruction is forwarded to the fetch instruction, the address is found to be matched but the data is not ready.
6. 6. The method of claim 5, wherein the re-execution event is the data cache bank access conflict, and wherein the determining that a re-execution event of a memory access instruction occurred comprises: In response to the store operation and the fetch operation acting on the same cache line, it is determined that the data cache bank access conflict occurred.
7. 7. The method of claim 5, wherein the feedback ports include at least one of a fast feedback port and a slow feedback port, the fast feedback port being provided at a pipeline stage 1 of the fetch pipeline, the slow feedback port being provided at a pipeline stage 3 of the fetch pipeline, the determining a target feedback port from the preset at least one feedback port based on the re-execution event comprising at least one of: Responsive to the re-execution event being the translation look-aside buffer failure, regarding the fast feedback port as the target feedback port; Responding to the access instruction being a fetch instruction and the re-execution event being the data cache access conflict, and taking the fast feedback port as the target feedback port; responding to the access instruction being a fetch instruction and the re-execution event failing to allocate for the data cache access failure queue, and taking the slow feedback port as the target feedback port; and taking the slow feedback port as the target feedback port in response to the access instruction being a fetch instruction and the re-execution event being that the access instruction data is not ready.
8. 8. The method of claim 5, wherein the causing the reservation station to retransmit the memory instruction based on the retransmission request comprises at least one of: Causing the reservation station to retransmit the memory instruction after a preset first time interval if the re-execution event is that the translation look-aside buffer is invalid; enabling the reservation station to immediately resend the access instruction when the access instruction is the fetch instruction and the re-execution event is the data cache access conflict; When the reservation station determines that the data cache access invalidation queue is empty under the condition that the re-execution event is that the data cache access invalidation queue is full, retransmitting the access instruction; Enabling the reservation station to immediately resend the access instruction under the condition that the re-execution event is that the data cache access failure queue is full; and when the reservation station finds that the addresses match but the data are not ready when the re-execution event is that the deposit instruction corresponding to the access instruction is delivered before the access instruction, the access instruction is retransmitted after the corresponding deposit data generation is determined according to the found deposit queue number.
9. 9. The method of claim 1, wherein the causing the reservation station to retransmit the memory instruction based on the retransmission request comprises at least one of: causing the reservation station to immediately resend the access instruction if it is determined that the reservation station does not trigger the re-execution event again when the access instruction is re-executed; enabling the reservation station to immediately resend the access instruction under the condition that the event causing re-execution is determined to be capable of being solved within a preset duration; and enabling the reservation station to resend the access instruction after a preset second time interval under the condition that the re-execution event is determined to be solved in the second time interval.
10. 10. The method according to any of claims 1-9, wherein the retransmission request contains at least one of the following information: reserving a station index field; A type field; The stock queue number field.
11. 11. A method of re-execution of a memory access instruction, the method being applied to a reservation station, the method comprising: receiving a retransmission request, wherein the retransmission request is a request which is sent to the reservation station by a processor and is determined to be a re-execution event of a memory access instruction, a target feedback port is determined from at least one preset feedback port based on the re-execution event or a target pipeline level of the memory access instruction, and the request is sent to the reservation station based on the target feedback port; and retransmitting the access instruction based on the retransmission request.
12. 12. A re-execution apparatus for access instructions, the apparatus being applied to a processor, the apparatus comprising: determining a re-execution event of a memory access instruction, and determining a target feedback port from at least one preset feedback port based on the re-execution event or a target pipeline level of the memory access instruction; and sending a retransmission request to a reservation station through the target feedback port so that the reservation station retransmits the access instruction based on the retransmission request.
13. 13. A re-execution apparatus for access instructions, the apparatus being applied to a reservation station, the apparatus comprising: The receiving module is used for receiving a retransmission request, wherein the retransmission request is a request which is sent to the reservation station by a processor and is determined to be a re-execution event of a memory access instruction, a target feedback port is determined from at least one preset feedback port based on the re-execution event or a target pipeline level where the memory access instruction is located, and the request is sent to the reservation station based on the target feedback port; And the processing module is used for retransmitting the access instruction based on the retransmission request.
14. 14. An electronic device comprising a processor and a memory communicatively coupled to the processor; The memory stores computer-executable instructions; the processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1-10, 11.
15. 15. A storage medium having instructions stored therein, which when executed on an electronic device, cause the electronic device to perform the method of any one of claims 1-10, 11.
16. 16. A program product comprising at least one of a program, instructions, characterized in that the at least one of a program, instructions, when executed by an electronic device, implements the steps of the method of any of claims 1-10, 11.

Description

Re-execution method, device and equipment of access instruction and storage medium Technical Field The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for re-executing a memory access instruction. Background With the development of computer processor technology, the performance of a processor access system has increasingly greater impact on processor performance. The increase of the access speed of the processor storage system is not matched with the increase of the operation speed of the processor, and the access speed severely restricts the further improvement of the performance of the processor. The blocking event of the memory access pipeline is reduced, and the execution is resumed as soon as possible after the cancel reason of the memory access operation to be canceled is solved, so that the blocking of the memory access instruction pipeline is reduced. Disclosure of Invention The present application aims to solve at least one of the technical problems in the related art to some extent. In a first aspect, the application provides a re-execution method of a memory access instruction, which comprises the steps of determining that a re-execution event of the memory access instruction occurs, determining a target feedback port from at least one preset feedback port based on the re-execution event or a target pipeline level where the memory access instruction is located, and sending a re-sending request to a reservation station through the target feedback port so that the reservation station re-sends the memory access instruction based on the re-sending request. In one implementation, each feedback port corresponds to at least one pipeline stage, the pipeline stages corresponding to different feedback ports are different, and the determining of the target feedback port from a plurality of preset feedback ports based on the target pipeline stage where the memory access instruction is located includes taking the feedback port corresponding to the target pipeline stage as the target feedback port. In an optional implementation manner, the access instruction is an access instruction, the access pipeline corresponding to the access instruction comprises four pipeline stages, the feedback port comprises a fast feedback port and a slow feedback port, the fast feedback port is arranged at a pipeline stage 1 of the access pipeline, the slow feedback port is arranged at a pipeline stage 3 of the access pipeline, the feedback port corresponding to the target pipeline stage is used as the target feedback port, and the method comprises the steps of determining that the target pipeline stage is a pipeline stage 0 or a pipeline stage 1 of the access pipeline, using the fast feedback port as the target feedback port, or determining that the target pipeline stage is a pipeline stage 2 or a pipeline stage 3 of the access pipeline, and using the slow feedback port as the target feedback port. In an optional implementation manner, the access instruction is a stock instruction, the stock pipeline corresponding to the stock instruction comprises four pipeline stages, the feedback port comprises a stock retransmission feedback port, the stock retransmission feedback port is arranged at the pipeline stage 1, and the determining of the target feedback port from a plurality of preset feedback ports based on the target pipeline stage where the access instruction is located comprises determining that the target pipeline stage is the pipeline stage 0 or the pipeline stage 1 of the stock pipeline, and taking the stock retransmission feedback port as the target feedback port. In one implementation, the re-execution event includes at least one of a translation look-aside buffer miss, a data cache bank access conflict, a data cache memory access miss queue full, and an address match found but data not ready when a store instruction corresponding to a fetch instruction is forwarded to the fetch instruction. In one implementation, the causing the reservation station to resend the access instruction based on the resend request includes at least one of causing the reservation station to resend the access instruction after a preset first time interval if the re-execution event is the translation look-aside buffer failure, causing the reservation station to resend the access instruction immediately if the access instruction is the fetch instruction and the re-execution event is the data cache bank access conflict, causing the reservation station to resend the access instruction immediately if the re-execution event is the data cache look-aside buffer failure queue full, resending the access instruction if it is determined that there is an empty entry in the data cache look-aside buffer, causing the reservation station to resend the access instruction immediately if the re-execution event is the data cache look-aside buffer failure queue full, causing