CN-122018998-A - EEPROM chip driving method and device

Abstract

The invention discloses an EEPROM chip driving method and device, the EEPROM chip driving method comprises determining a read/write/query process action sequence array, extracting basic time sequence actions from original driving time sequence actions for driving an EEPROM chip as basic instructions, combining a plurality of basic instructions as combined instructions, decomposing into a read process action sequence array, a write process action sequence array and a query process action sequence array respectively comprising a plurality of combined instructions according to the read/write/query process of the EEPROM chip, and forming corresponding driving programs according to different process action sequence arrays for driving the EEPROM chip. The EEPROM chip driving method is convenient for code maintenance, improves program readability, distinguishes the timing of actions and time sequences, and is easy to adjust the execution speed and sequence of each action according to different chips.

Inventors

• LIU QINGMING
• LI WENYANG

Assignees

• 青岛海信日立空调系统有限公司

Dates

Publication Date

20260512

Application Date

20241111

Claims (10)

1. 1. An EEPROM chip driving method, comprising: Determining a read/write/query process action sequence array, comprising: Extracting a basic time sequence action from the original driving time sequence action of driving an EEPROM chip as a basic instruction, wherein the basic instruction is a single instruction for controlling an MCU port connected with a serial data line pin SDA, a serial clock line pin SCL and a write protection pin WP of the EEPROM chip; Combining a plurality of basic instructions as combined instructions, wherein the combined instructions repeatedly appear in the driving time sequence action for a plurality of times; according to the read/write/query process of the EEPROM chip, decomposing into a read process action sequence array, a write process action sequence array and a query process action sequence array which respectively comprise a plurality of combined instructions; And forming a corresponding driving program for driving the EEPROM chip according to different process action sequence arrays.
2. 2. The EEPROM chip driving method according to claim 1, wherein the basic instructions at least include: Modifying the value of the direction register of the pin, setting or clearing the pin, and reading the value of the pin.
3. 3. The EEPROM chip driving method according to claim 1, wherein in determining the array of the read/write/query process action sequences, further comprising: Setting a process variable for recording and controlling a state of a driver execution process; Setting a virtual instruction, wherein the virtual instruction is used for a code segment formed by combining specific logic and calculation tasks in the process of completing reading and writing.
4. 4. The EEPROM chip driving method according to claim 1, wherein each of the base instruction and the combination instruction is numbered simultaneously when the base instruction and the combination instruction are formed.
5. 5. The EEPROM chip driving method according to claim 2, wherein the basic instruction comprises: A first basic instruction, configured to set a value of a direction register of a pin SDA, so that the direction register of the pin SDA is an output; A second basic instruction, configured to set a value of a direction register of a pin SDA, so that the direction register of the pin SDA is an input; a third basic instruction, configured to set a value of a direction register of a pin SCL, so that the direction register of the pin SCL is an output; A fourth base instruction for setting a value of a direction register of pin SCL, causing the direction register of pin SCL to be an input.
6. 6. The EEPROM chip driving method according to claim 2, wherein the basic instructions further comprise: a fifth base instruction for enabling write protection, setting the write protection pin WP; A sixth basic instruction for turning off write protection, clears the write protect pin WP.
7. 7. The EEPROM chip driving method according to claim 2, wherein the basic instructions further comprise: a seventh basic instruction for reading the state of the SDA line connected to the pin SDA.
8. 8. The EEPROM chip driving method according to claim 1, wherein the combination instruction at least includes: A first combination instruction for setting an I2C bus start signal; A second combined instruction for setting an I2C bus stop signal; a third combined instruction for transmitting one data bit; a fourth combined instruction for receiving a data bit; a fifth combination instruction for checking whether the response signal ACK is legal or not when writing data or transmitting chip select data; A sixth combination instruction for responding to the response signal ACK on the I2C bus when reading the data, and sending a non-response signal NACK when the last data is read; A seventh combined instruction to establish the normal state of pins SCL, SDA and WP; And an eighth combined instruction for setting the EEPROM chip to an idle state.
9. 9. The EEPROM chip driving method according to claim 8, wherein the seventh combination instruction is specifically for: Setting pins SCL and SDA as input ports, setting the output of an output register as 0, and closing write protection during write operation; The eighth combination instruction is specifically configured to: the pins SCL and SDA are set as input ports, the output of the output register is set to 0, and write protection is enabled.
10. 10. An EEPROM chip driving apparatus, comprising: Processor, and A memory storing processor-executable program code that, when executed by a processor, implements the EEPROM chip driving method of any one of claims 1 to 9.

Description

EEPROM chip driving method and device Technical Field The present invention relates to the field of memory control technologies, and in particular, to a method and an apparatus for driving an EEPROM chip. Background EEPROM (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY, electrically erasable programmable read-only memory) is a memory chip that does not lose data after power down. The EEPROM chip can be directly used for controlling the erasing and writing on a computer or special equipment by using a circuit, and does not need to be erased and written by using external equipment, namely the equipment can be erased and written at any time in the running process, the data can be modified according to the unit of bytes, the whole chip is not required to be erased, and the EEPROM chip is generally used for storing some configuration information so as to be loaded when the system is powered on again. When a plurality of enterprises use EEPROM chip storage equipment to configure and run data, drivers of an IO port simulation mode are used to be used, the processing of clock signals and data signals by a plurality of related software does not accord with the specification of an I2C bus protocol, and when different models and manufacturers are replaced for supply, poor compatibility is easy to occur for adjusting time sequence, so that software accidents are caused. The traditional IO port drives the software function of an I2C (Inter-INTEGRATED CIRCUIT, integrated circuit bus) bus to be relatively trivial, the function is relatively more, the operation and the operation speed of the IO port are mixed in the same code section, the maintenance and the test need to carry out integral browsing and analysis on the code, and the efficiency is low, the readability is poor, and the error is easy to make. Disclosure of Invention Aiming at the problems pointed out in the background art, the application provides an EEPROM chip driving method, which adopts an instruction type driving framework to decompose the read-write process of the EEPROM into an action sequence array formed by a plurality of instructions, is convenient for code maintenance, improves the program readability, distinguishes the timing of actions and time sequences, and is easy to adjust the execution speed and the sequence of each action according to different EEPROM chips. In order to achieve the aim of the invention, the invention is realized by adopting the following technical scheme: Some embodiments of the application relate to an EEPROM chip driving method, comprising: Determining a read/write/query process action sequence array, comprising: Extracting a basic time sequence action from the original driving time sequence action of driving an EEPROM chip as a basic instruction, wherein the basic instruction is a single instruction for controlling an MCU port connected with a serial data line pin SDA, a serial clock line pin SCL and a write protection pin WP of the EEPROM chip; Combining a plurality of basic instructions as combined instructions, wherein the combined instructions repeatedly appear in the driving time sequence action for a plurality of times; according to the read/write/query process of the EEPROM chip, decomposing into a read process action sequence array, a write process action sequence array and a query process action sequence array which respectively comprise a plurality of combined instructions; And forming a corresponding driving program for driving the EEPROM chip according to different process action sequence arrays. The technical scheme related to the embodiment has the following beneficial effects or advantages: According to the technical scheme, basic instructions are decomposed from original driving time sequence actions, a plurality of basic instructions are combined into combined instructions to form an instruction type driving framework, basic actions of an EEPROM and repeated I2C bus time sequence actions are abstracted, coding is conducted in a concentrated mode according to a reading/writing/inquiring process, a reading process action sequence array, a writing process action sequence array and an inquiring process action sequence array are formed, action standardization is achieved, understanding and management are easy, design is simplified, searching problems are easier, meanwhile software complexity is reduced, software maintainability is improved, later upgrading is easy, and new functions are added. And the instruction type driving framework separates the timing of actions and time sequences, so that the interval time (namely the execution speed) and the sequence among the actions can be conveniently adjusted according to the timing requirements of different chips, new functions can be conveniently added, and the software testing efficiency is improved. In some embodiments of the application, the base instructions include at least: Modifying the value of the direction register of the pin, setting or clearing t