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CN-122019017-A - Repeated assignment statement processing method, electronic device and medium

CN122019017ACN 122019017 ACN122019017 ACN 122019017ACN-122019017-A

Abstract

The invention relates to the technical field of chip design and verification, in particular to a repeated assignment statement processing method, electronic equipment and medium, wherein the method comprises the steps of S1, {A 1 ,A 2 ,...,A j ,...,A J },A j ={A 1 j ,A 2 j ,A 3 j ,A 4 j }; steps S2 of obtaining repeated assignment information to be processed in a source code, If A 2 j is greater than the preset threshold and A 4 j is the preset optimized element type, executing step S3 based on the corresponding A j , wherein the step S3, setting a preset interface calling instruction for A j , and step S4, When a preset interface call instruction corresponding to a j is executed, a standard memory data block of each element in a 3 j is generated based on a 3 j and a 4 j , and the corresponding standard memory data block is stored to each corresponding target storage location based on a start location corresponding to a 1 j and a 2 j . the invention improves the compiling efficiency, the simulation performance and the expandability.

Inventors

  • CHEN XINGBO
  • ZHANG BANGQUAN
  • ZHOU HUANTAO
  • HONG JIANGTAO

Assignees

  • 上海合见工业软件集团股份有限公司
  • 成都融见软件科技有限公司

Dates

Publication Date
20260512
Application Date
20260413

Claims (10)

  1. 1. A method of processing a repeat assignment statement, comprising: Step S1, in a grammar analysis stage of a compiler, obtaining to-be-processed repeated assignment information { A 1 ,A 2 ,...,A j ,...,A J } in a source code, wherein A j is a target variable corresponding to a j-th to-be-processed repeated assignment information ,A j ={A 1 j ,A 2 j ,A 3 j ,A 4 j },A 1 j is A j , A 2 j is repeated assignment times corresponding to A j , A 3 j is a repeated value corresponding to A j , and A 4 j is a target variable type corresponding to A j ; Step S2, in the compiling process, if A 2 j is larger than a preset threshold value and A 4 j is a preset optimization element type, executing step S3 based on the corresponding A j ; Step S3, a preset interface calling instruction is set for A j ; Step S4, in the simulation process, when a preset interface call instruction corresponding to A j is executed, A 1 j ,A 2 j ,A 3 j ,A 4 is transmitted to a preset interface, standard memory data blocks of each element in A 3 j are generated based on A 3 j and A 4 j , and the corresponding standard memory data blocks are stored to each corresponding target storage position based on the starting position corresponding to A 1 j and A 2 j .
  2. 2. The method of claim 1, wherein the step of determining the position of the substrate comprises, The step S1 includes: Step S11, in the grammar analysis stage of the compiler, acquiring a to-be-processed repeated assignment statement in the source code, if the to-be-processed repeated assignment statement is of a single-layer single-value repeated type or a single-layer multi-value repeated type, executing the step S13, and if the to-be-processed repeated assignment statement is of a nested repeated type, executing the step S12; Step S12, converting the repeated assignment statement to be processed of the nested repeated type into a single-layer single-value repeated type or a single-layer multi-value repeated type repeated assignment statement, and executing the step S13; And S13, acquiring A 1 n ,A 2 n ,A 3 n ,A 4 n corresponding to the repeated assignment statement to be processed, generating corresponding A n , and generating { A 1 ,A 2 ,...,A n ,...,A N } based on all the A n .
  3. 3. The method of claim 1, wherein the step of determining the position of the substrate comprises, The target variable types include arrays, queues, and complexes, the arrays including static arrays and dynamic arrays.
  4. 4. The method of claim 1, wherein the step of determining the position of the substrate comprises, The preset optimization variable type comprises an array and a queue.
  5. 5. The method of claim 1, wherein the step of determining the position of the substrate comprises, In the step S4, the generating a standard memory data block of each element in a 3 j based on a 3 j and a 4 j includes: Step S41, calling the preset interface, converting each element in A 3 j into a memory storage format matched with the element type corresponding to A 4 j , generating a standard memory data block corresponding to each element in A 3 j , wherein the element type corresponding to A 4 j comprises a four-state logic type and a two-state logic type.
  6. 6. The method of claim 5, wherein the step of determining the position of the probe is performed, In the step S4, storing the corresponding standard memory data block to each corresponding target storage location based on the start location corresponding to a 1 j and a 2 j includes: Step S42, if A j is 'single-layer single-value repeat type', storing the corresponding standard memory data block to each corresponding target storage position by adopting a single-value filling mode; Step S43, if A j is a single-layer multi-value repetition type, the obtained multi-value sequence { value 1 ,value 2 ,...,value i ,...,value X },value i corresponding to A 3 j is the ith repetition value corresponding to A 3 j , the value range of i is 1 to X, and X is the number of repetition values corresponding to A 3 j ; Step S44, alternately storing the standard memory data block corresponding to each value i to each corresponding target storage location based on the sequence of the values 1 ,value 2 ,...,value i ,...,value X .
  7. 7. The method of claim 6, wherein the step of providing the first layer comprises, If the element data length corresponding to a 3 j is smaller than the preset length threshold, in the step S42 and the step S44, storing the standard memory data block to each corresponding target storage position by adopting a direct assignment mode; If the element data length corresponding to a 3 j is greater than the preset length threshold, in step S42 and step S44, the standard memory data block is stored to each corresponding target storage location by using a memory copy manner.
  8. 8. The method of claim 6, wherein the step of providing the first layer comprises, In the step S42 and the step S44, the next target storage location is automatically located by the address self-increasing mechanism based on the start address of the target variable until the a 2 j target storage locations are located.
  9. 9. An electronic device, comprising: At least one processor; And a memory communicatively coupled to the at least one processor; wherein the memory stores instructions for execution by the at least one processor, the instructions being configured to perform the method of any one of claims 1-8.
  10. 10. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method according to any of claims 1-8.

Description

Repeated assignment statement processing method, electronic device and medium Technical Field The present invention relates to the field of chip design and verification technologies, and in particular, to a method for processing repeated assignment statement, an electronic device, and a medium. Background In hardware description languages, such as System Verilog, when a assignment pattern (ASSIGNMENT PATTERN) is used to repeatedly assign values to a container such as a large-scale array, conventional implementations suffer from at least the following drawbacks (1) for large-scale repeated assignment statements, a conventional compiler adopts a grammar expansion strategy to generate a large number of redundant intermediate codes. For example, for an assignment statement shaped as q= ' {10000{4' b1101}, a conventional compiler will develop it as an independent assignment statement corresponding to the number of container elements (e.g., q [0] = 4' b1101, q [1] = 4' b1101,..q [9999] = 4' b 1101), resulting in a linear increase in compile time and array size, a significant increase in large-scale design compile time, a dramatic expansion of Abstract Syntax Trees (AST) and Intermediate Representations (IR), and a heavy burden in the subsequent optimization stage, resulting in a low compile efficiency. (2) The simulator needs to perform thousands of assignment operations one by one, causing unnecessary runtime overhead. Each assignment may trigger the simulation event scheduling, resulting in reduced simulation efficiency, inefficient memory access patterns, and poor simulation performance. (3) The generated intermediate code is huge in size, the storage and transmission cost is increased, a very large-scale array (such as a megabit wide register) cannot be processed, and the application of System Verilog in complex SoC verification and large-scale IP design is limited, so that the expandability is poor. Therefore, how to intelligently process repeated assignment sentences, improving compiling efficiency, simulation performance and expandability becomes a technical problem to be solved. Disclosure of Invention The invention aims to provide a repeated assignment statement processing method, electronic equipment and medium, which improve compiling efficiency, simulation performance and expandability. According to a first aspect of the present invention, there is provided a repeated assignment statement processing method, including: Step S1, in a grammar analysis stage of a compiler, obtaining to-be-processed repeated assignment information { A 1,A2,...,Aj,...,AJ } in a source code, wherein A j is a target variable corresponding to a j-th to-be-processed repeated assignment information ,Aj={A1j,A2j,A3j,A4j},A1j is A j, A 2j is repeated assignment times corresponding to A j, A 3j is a repeated value corresponding to A j, and A 4j is a target variable type corresponding to A j; Step S2, in the compiling process, if A 2j is larger than a preset threshold value and A 4j is a preset optimization element type, executing step S3 based on the corresponding A j; Step S3, a preset interface calling instruction is set for A j; Step S4, in the simulation process, when a preset interface call instruction corresponding to A j is executed, A 1j,A2j,A3j,A4 is transmitted to a preset interface, standard memory data blocks of each element in A 3j are generated based on A 3j and A 4j, and the corresponding standard memory data blocks are stored to each corresponding target storage position based on the starting position corresponding to A 1j and A 2j. According to a second aspect of the present invention there is provided an electronic device comprising at least one processor and a memory communicatively coupled to the at least one processor, wherein the memory stores instructions for execution by the at least one processor, the instructions being arranged to perform the method of the first aspect of the present invention. According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention. Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the repeated assignment statement processing method, the electronic equipment and the medium can achieve quite technical progress and practicality, have wide industrial utilization value, and have at least the following beneficial effects: According to the invention, the preset interface is set, so that the to-be-processed repeated assignment statement with the repeated assignment times larger than the preset threshold value is not directly unfolded in the compiling stage, the corresponding preset interface calling instruction is set, the repeated assignment operation is executed based on the preset interface calling instruction in the simulation stage, the compiling complexity o