CN-122019075-A - Heterogeneous many-core resource scheduling method apparatus, device, medium, and product

CN122019075ACN 122019075 ACN122019075 ACN 122019075ACN-122019075-A

Abstract

The invention relates to the technical field of data flow programming and discloses a heterogeneous many-core resource scheduling method, a device, equipment, a medium and a product, wherein the method is applied to a host side and comprises the steps of obtaining a target scheduling instruction of a target chip, wherein the target scheduling instruction is obtained through a target programming interface, and the target programming interface is used for configuring the number of computing core arrays in a cooperation group and the computing tasks of different computing core arrays in the cooperation group; determining cooperative group information, identification information of different target computing core arrays in the cooperative group and computing task information executed by each target computing core array based on the target scheduling instruction, starting a plurality of target computing core arrays in the same cooperative group to execute computing tasks at the same time, generating target instructions based on the cooperative group information, the identification information of the different target computing core arrays in the cooperative group and the computing task information executed by each cooperative group, and transmitting the target instructions to a target chip of a device side for execution.

Inventors

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Assignees

太初(无锡)电子科技有限公司

Dates

Publication Date: 20260512
Application Date: 20251226

Claims (10)

1. The heterogeneous many-core resource scheduling method is characterized by being applied to a host end, wherein the host end is connected with a device end, the device end is integrated with a target chip, the target chip comprises a plurality of computing core arrays, each computing core array comprises a plurality of computing cores, and the method comprises the following steps: acquiring a target scheduling instruction of a target chip, wherein the target scheduling instruction is acquired through a target programming interface, and the target programming interface is used for configuring the number of computing core arrays in a cooperation group and computing tasks of different computing core arrays in the cooperation group; Determining information of a collaboration group, identification information of different target computing core arrays in the collaboration group and computing task information executed by each target computing core array based on the target scheduling instruction, wherein each collaboration group comprises a plurality of target computing core arrays to be scheduled, and a plurality of target computing core arrays in the same collaboration group simultaneously start executing computing tasks; generating target instructions based on the collaboration group information, identification information of different target computing core arrays in the collaboration groups and computing task information executed by each collaboration group; and sending the target instruction to the target chip of the equipment end for execution.
2. The method of claim 1, wherein the step of generating target instructions based on the collaboration group information, identification information of different target compute core arrays in the collaboration group, and task information performed by each target compute core array, comprises: based on a pre-constructed synchronization primitive interface, acquiring synchronization operation instructions of a plurality of target computing core arrays in a collaboration group, wherein the synchronization primitive interface is used for configuring synchronization control rule information of different target computing core arrays in each collaboration group; and generating the target instruction based on the synchronous operation instruction, the collaboration group information, the identification information of the target computing core arrays and the task information executed by each target computing core array.
3. The method of claim 2, wherein the host side is deployed with a heterogeneous many-core programming model, the heterogeneous many-core programming model comprising a resource pool, the target programming interface, and a compiler, the resource pool configured to abstract package hardware resources of a target chip.
4. The method of claim 3, wherein the generating the target instruction based on the synchronization operation instruction, the collaboration group information, identification information of the plurality of target compute core arrays, and task information performed by each target compute core array comprises: generating a computing function based on the synchronous operation instruction, the collaboration group information, the identification information of the target computing core arrays and task information executed by each target computing core array, wherein the computing function is a carrier for bearing target computing task computing logic; and compiling the calculation function by using the compiler to obtain the target instruction.
5. The method of claim 2, wherein the synchronous operation instructions comprise a blocking full synchronization instruction, a non-blocking full synchronization instruction, a blocking partial core synchronization instruction, and a non-blocking partial core synchronization instruction.
6. The method according to any one of claims 1 to 5, wherein after the step of sending the target instruction to the target chip at the device side, the method further comprises: Obtaining a calculation result output by the target chip; and storing the calculation result into a target database.
7. A heterogeneous many-core resource scheduling apparatus for performing the method of claim 1, the apparatus comprising: The first acquisition module is used for acquiring target scheduling instructions of a target chip, wherein the target scheduling instructions are acquired through a target programming interface, and the target programming interface is used for configuring the number of computing core arrays in a cooperation group and computing tasks of different computing core arrays in the cooperation group; The first determining module is used for determining information of a collaboration group, identification information of different target computing core arrays in the collaboration group and computing task information executed by each target computing core array based on the target scheduling instruction, wherein each collaboration group comprises a plurality of target computing core arrays to be scheduled, and a plurality of target computing core arrays in the same collaboration group simultaneously start executing computing tasks; the second determining module is used for generating target instructions based on the information of the collaboration groups, the identification information of different target computing core arrays in the collaboration groups and the computing task information executed by each collaboration group; And the sending module is used for sending the target instruction to the target chip of the equipment end for execution.
8. An electronic device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the heterogeneous many-core resource scheduling method of any of claims 1 to 6 by executing the computer instructions.
9. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the heterogeneous many-core resource scheduling method of any of claims 1 to 6.
10. A computer program product comprising computer instructions for causing a computer to perform the heterogeneous many-core resource scheduling method of any of claims 1 to 6.

Description

Heterogeneous many-core resource scheduling method apparatus, device, medium, and product Technical Field The invention relates to the technical field of data stream programming, in particular to a heterogeneous many-core resource scheduling method apparatus, devices, media, and articles. Background Currently, artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) is continuously pushing digitization and intellectualization to deep development, and wider application and more profound technological transformation are brought to more and more industries. With the complexity of AI, model structures and the continuous rise of training and reasoning demands, computing resources are facing unprecedented challenges. An artificial intelligence system represented by a large language model (Large Language Model, LLM) shows explosive growth of the demand for computational resources, and a heterogeneous many-core architecture becomes the mainstream, but the existing mainstream has a plurality of defects on the resource scheduling mode. In the related technology, a single computing core array is used as a main scheduling object, slave cores are automatically mapped by a compiler, explicit multi-core scheduling and cooperative control semantics are lacked, cooperative execution of a multi-slave core array is not supported, a cross-heterogeneous core unified scheduling mechanism is also not supported, hardware parallel computing power is difficult to fully release, and the dependence control requirement of complex parallel tasks cannot be met. Disclosure of Invention The invention provides a heterogeneous many-core resource scheduling method, a device, equipment, a medium and a product, which are used for solving the problems that in the related art, by taking a single computing core array as a main scheduling object, the cooperative execution of a multi-slave core array is not supported, a cross-heterogeneous core unified scheduling mechanism is not available, the hardware parallel computing power is difficult to fully release, and the dependence control requirement of complex parallel tasks cannot be met. The invention provides a heterogeneous many-core resource scheduling method, which is applied to a host side, wherein the host side is connected with a device side, the device side is integrated with a target chip, the target chip comprises a plurality of computing core arrays, each computing core array comprises a plurality of computing cores, the method comprises the steps of obtaining target scheduling instructions of the target chip, the target scheduling instructions are obtained through target programming interfaces, the target programming interfaces are used for configuring the number of the computing core arrays in a cooperative group and computing tasks of different computing core arrays in the cooperative group, determining information of the cooperative group, identification information of different target computing core arrays in the cooperative group and computing task information executed by each target computing core array based on the target scheduling instructions, each cooperative group comprises a plurality of target computing core arrays needing to be scheduled, the plurality of target computing core arrays in the same cooperative group simultaneously start executing computing tasks, generating target instructions based on the information of the cooperative group, the identification information of the different target computing core arrays in the cooperative group and the computing task information executed by each cooperative group, and transmitting the target instructions to the target chip of the device side to execute. The heterogeneous many-core resource scheduling method provided by the invention relies on the connection architecture of a host end and a device end integrated with a target chip, and aims at the hardware characteristics of a plurality of computing core arrays contained in the target chip, and a target scheduling instruction is acquired through a specially designed target programming interface, the interface can explicitly configure the number of computing core arrays in a cooperative group and the computing tasks of different computing core arrays, so that the passive automatic mapping scheduling mode in the related technology is thoroughly changed, the semantic support of explicit multi-core scheduling and cooperative control is completed, on the basis, the host end accurately determines the cooperative group information, the identification information of each target computing core array and the corresponding computing task information based on the target scheduling instruction, definitely brings a plurality of computing core arrays to be scheduled into the same cooperative group and ensures that a plurality of computing core arrays in the group simultaneously start execution tasks, the technology that the plurality of computing core arrays can not be pulled up for execution sim