CN-122019079-A - Multi-task scheduling method and scheduling control unit of multi-core processor architecture

CN122019079ACN 122019079 ACN122019079 ACN 122019079ACN-122019079-A

Abstract

The application discloses a multi-task scheduling method and a scheduling control unit of a multi-core processor architecture, and relates to the technical field of wireless communication and processor scheduling. The method comprises the steps of system initialization, task distribution judgment, task queue management, multi-core task execution and response, wherein a general RISC core starts a scheduling judgment flow after receiving wireless communication calculation task information, task information is issued to a dynamic reconfigurable task instruction issuing unit after judgment is completed, the dynamic reconfigurable task instruction issuing unit writes the task information into a task queue memory according to a queue ID, the multi-core task execution and response comprises the steps of monitoring the corresponding task queue memory state in real time by an external multi-core, reading the task information and executing when a task to be executed is detected, and refreshing the task queue memory state after completion. The application is directed to a multi-core processor architecture processed in the wireless communication field, and flexible expansion and combination among multiple cores are realized by designing a programmable task scheduling unit and programming by instructions according to application scene requirements.

Inventors

SHAN RUI
HU JIAHAO
YANG NINGYU
YANG BOWEN

Assignees

西安邮电大学

Dates

Publication Date: 20260512
Application Date: 20251231

Claims (6)

1. A method for multi-task scheduling in a multi-core processor architecture, comprising: The method comprises the following steps of S1, initializing a system, namely initializing a peripheral module after a general RISC core is started, initializing an empty and full state of each task queue memory by a dynamic reconfigurable task instruction issuing unit, setting a task queue state register to be in an empty state, and feeding back an initialization completion signal to the general RISC core through a system bus; S2, task distribution judgment, namely an upper computer transmits wireless communication calculation task information to Config_RF of a general RISC core, the general RISC core starts a scheduling judgment flow after reading the task information to RF, and after judgment, the general RISC core transmits the task information to the dynamic reconfigurable task instruction transmitting unit through the system bus, and bus resources are released immediately after distribution is completed; S3, task queue management, wherein the dynamic reconfigurable task instruction issuing unit writes the task information into the corresponding task queue memory according to the queue ID in the task information issued by the general RISC core; And S4, the multi-core task executes and responds to the state of the corresponding task queue memory when the external processor verifies, when the task to be executed in the task queue memory is detected, the task information is read from the queue and the task is executed, after the execution is completed, the state of the task queue memory is refreshed, and the general RISC core sends new task information according to the real-time state of the task queue state register.
2. The multi-task scheduling method of a multi-core processor architecture according to claim 1, wherein the scheduling determination flow comprises: S2.1, reading task basic information stored in the Config_RF, wherein the task basic information comprises a starting address of a task instruction in the DDR, the total number of the instructions and the task type; S2.2, acquiring the real-time state of a register in the dynamic reconfigurable task instruction issuing unit through the system bus; S2.3, dynamically determining a target task queue memory adapting to the complexity and the queue state of the task according to a scheduling algorithm.
3. The method for multi-task scheduling of a multi-core processor architecture of claim 2, wherein the scheduling algorithm comprises: S2.3.1, task information analysis and state acquisition, namely, a general RISC core receives a task request issued by an APB, extracts the total number N of task instructions and the task type T, reads three key states of a register in the dynamic reconfigurable task instruction issuing unit through the system bus, namely, an instruction number threshold value TH processed by a single processor core and stored in an instruction number threshold value register, and the current task number in a task storage queue FIFO bound by 4 external processor cores and stored in a queue task count register A queue idle or active state stored by the task queue status register; S2.3.2 instruction number threshold determination and processing path selection, checking if N is less than or equal to TH and T=0, i.e. when the current task is a low/medium load task If (if) Less than the FIFO depth threshold, assigning tasks to the CORE0 queue if When the FIFO depth threshold is reached, traversing the CORE 1-3 to screen the queue in the idle state, if the queue is idle, distributing the task to the CORE queue, and if the queue is not idle, checking If the FIFO depth threshold value is smaller than the FIFO depth threshold value, the tasks are distributed to the corresponding CORE queues, if the FIFO depth threshold value is reached, the task distribution is performed until an idle queue is found, if N > TH or T=1, namely, when the current task is a high-load task, a dynamic expansion mechanism is triggered, the queues in the idle state are screened in the CORE 1-3 queues, the CORE queues are distributed, and if the queues are not idle, the task distribution is performed again until the idle queue is found; and S2.3.3, task allocation and state update, namely writing task information into a target FIFO, wherein the task information comprises a DDR initial address and the total number N of instructions, and synchronously updating a corresponding queue task count register.
4. A multi-task scheduling control unit of a multi-core processor architecture, characterized in that the scheduling control unit applies the method of any one of claims 1-3, comprising: The general RISC core is used for carrying out task allocation, load balancing and running state regulation and control on the multi-core processor; The dynamic reconfigurable task instruction issuing unit is used for issuing tasks and perceiving load states in real time and comprises a task queue memory, a task information register set, a configuration register set, a control unit and a control unit, wherein the task queue memory is used for storing special task information to be issued to an external processor core and comprises 4 isomorphic task storage queue FIFOs; The peripheral module comprises a RAM, a CLINT, a UART and a GPIO, wherein the RAM is used for caching original data and intermediate results, the CLINT is used for timing interrupt of a system and task queue emptying, and the UART and the GPIO are used for debugging and peripheral control.
5. The multi-task scheduling control unit of a multi-core processor architecture according to claim 4, wherein the configuration register set includes a task queue status register for storing a full empty status of each task queue, an instruction number threshold register for storing an instruction number threshold of a single processor core processing task, a queue task count register for storing a current task number of 4 task storage queue FIFOs, a task DDR start address register for storing a start address of a task to be executed in an external DDR memory, a task instruction number register for storing a total number of external processor core customized instructions contained in the current task, a FIFO ID configuration register for storing a target task queue number corresponding to a task to be issued, a FIFO write enable register for writing task information to the task storage queue FIFOs, and a FIFO refresh register for forcedly refreshing storage data of all the task storage queues FIFOs for resetting when a task is switched or abnormally processed.
6. The multi-task scheduling control unit of claim 4, wherein the task store queue FIFO has a data bit width of 64 bits and a depth of 16 entries.

Description

Multi-task scheduling method and scheduling control unit of multi-core processor architecture Technical Field The present application relates to the field of wireless communication and processor scheduling technologies, and in particular, to a multi-task scheduling method and a scheduling control unit for a multi-core processor architecture. Background With the popularization of 5G technology, the wireless communication computing process faces the challenges of computing power and real-time caused by complex scenes such as ultra-dense networking and multi-standard compatibility, and the single-core architecture has difficulty in meeting the demands of massive concurrent data processing and differentiated tasks. In the prior art, although part of the multi-core architecture has the capability of basic parallel processing, static scheduling or a simple load balancing strategy is adopted, the dynamic characteristics of wireless communication tasks are difficult to adapt, the task allocation cannot be adjusted in real time according to the task priority and the core load state, meanwhile, the calculation tasks are not fully excavated due to insufficient fine granularity disassembly of the calculation tasks, the serial processing bottleneck is not thoroughly broken through, the problems cause low utilization rate of processor core resources, unbalanced states of overload operation of part of processor cores and idle waste of other cores occur, the requirements of the wireless communication scene on instantaneity and energy efficiency ratio are difficult to meet finally, and the application efficiency of the multi-core architecture in complex communication scenes is limited. Disclosure of Invention The embodiment of the application provides a multi-task scheduling method and a scheduling control unit of a multi-core processor architecture, which are used for solving the problems in the prior art. In one aspect, an embodiment of the present application provides a multi-task scheduling method for a multi-core processor architecture, including: S1, initializing a system, namely initializing a peripheral module after a general RISC (reduced instruction set computer) core is started, initializing an empty and full state of each task queue memory by a dynamic reconfigurable task instruction issuing unit, setting a task queue state register to be in an empty state, feeding back an initialization completion signal to the general RISC core through a system bus, and waiting for receiving task information in the task queue memory by an external processor core. S2, task distribution judgment, namely the upper computer transmits wireless communication calculation task information to Config_RF (configuration register set) of the general RISC core, the general RISC core starts a scheduling judgment flow after reading the task information to RF (general register set), and after judgment, the general RISC core transmits the task information to the dynamic reconfigurable task instruction transmitting unit through a system bus, and bus resources are released immediately after distribution is completed. In detail, the scheduling determination flow includes: S2.1, reading task basic information stored in Config_RF, wherein the task basic information comprises a starting address of a task instruction in DDR (double speed synchronous dynamic random access memory), the total number of instructions and the task type. S2.2, acquiring the real-time state of a register in the dynamic reconfigurable task instruction issuing unit through a system bus. S2.3, dynamically determining a target task queue memory adapting to the complexity and the queue state of the task according to a scheduling algorithm. In detail, the scheduling algorithm includes: S2.3.1 task information analysis and state acquisition, namely, a general RISC core receives a task request issued by an APB (peripheral bus), extracts the total number N of task instructions and the task type T, reads three key states of a register in a dynamic reconfigurable task instruction issuing unit through a system bus, namely, an instruction number threshold value TH processed by a single processor core and stored in an instruction number threshold value register, and the current task number in task storage queue FIFO (first-in first-out memory) bound by 4 external processor cores and stored in a queue task count register A queue idle or active state stored by the task queue status register; S2.3.2 instruction number threshold determination and processing path selection, checking if N is less than or equal to TH and T=0, i.e. when the current task is a low/medium load task If (if)Less than the FIFO depth threshold, the task is allocated to the CORE0 (external processor CORE) queue ifWhen the FIFO depth threshold is reached, traversing the CORE 1-3 to screen the queue in the idle state, if the queue is idle, distributing the task to the CORE queue, and if the queue is not idle, checkingIf the