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CN-122019086-A - Interrupt processing method for CPU simulation

CN122019086ACN 122019086 ACN122019086 ACN 122019086ACN-122019086-A

Abstract

Compared with the prior art, the method adds an interrupt identifier in a target program, and actively acquires an interrupt signal and sets the interrupt signal by a firmware program, thereby effectively avoiding global variable address conflict caused by asynchronous execution of the program, realizing the mechanism that the interrupt program is immediately executed and the main program waits for the completion of the interrupt program according to the interrupt identifier and the interrupt signal, avoiding the simultaneous operation of registers of two types of programs, ensuring the atomicity of configuration logic, avoiding concurrent conflict, conforming to sequential logic with interrupt response priority, and improving the reliability of simulation.

Inventors

  • WU SHUANG

Assignees

  • 沐曦科技(成都)有限公司

Dates

Publication Date
20260512
Application Date
20260119

Claims (8)

  1. 1. An interrupt handling method for CPU emulation, the method comprising: S201, when the interrupt mark in the received target program is a first preset value, executing the target program, and setting an interrupt signal corresponding to a CPU simulation module to be a second preset level after the execution of the target program is completed; S202, when the received interrupt identifier in the target program is a second preset value, acquiring an interrupt signal corresponding to the CPU simulation module; S203, if the interrupt signal is at a first preset level, executing the target program; S204, if the interrupt signal is at the first preset level, the target program is executed after waiting for the interrupt signal to be changed to the second preset level.
  2. 2. The interrupt processing method according to claim 1, wherein the target program is an interrupt program or a main program; the interrupt program comprises a first operation function, and the main program comprises a second operation function; the interrupt identifier included in the first operation function is a first preset value, and the interrupt identifier included in the second operation function is a second preset value.
  3. 3. The interrupt processing method according to claim 2, wherein the first operation function and the second operation function each correspond to an operation task in a CPU emulation module, and when executed, each call an operation task in the CPU emulation module to operate the register.
  4. 4. The interrupt processing method according to claim 1, wherein the target program belongs to a firmware program, the firmware program, an interface interaction layer and a calling function are compiled to obtain a dynamic library, and the CPU simulation module loads the dynamic library and is connected with the dynamic library through a preset interface.
  5. 5. The interrupt processing method of claim 4, wherein the number of CPU emulation modules is M, M being a positive integer; Correspondingly, 2 xM dynamic libraries are obtained by copying, and the memory address spaces corresponding to the 2 xM dynamic libraries are different; the m-th CPU simulation module is bound with the 2m-1 th dynamic library and the 2 m-th dynamic library, wherein m is an integer in the range of [1, M ].
  6. 6. The interrupt processing method according to claim 5, wherein the 2m-1 th dynamic library and the 2 m-th dynamic library correspond to an mth independent storage area, and the mth independent storage area is used for supporting data interaction of global variables that the 2m-1 st dynamic library and the 2 m-th dynamic library need to share.
  7. 7. The interrupt processing method of claim 6 wherein the 2m-1 st dynamic library and the 2 m-th dynamic library do not require a shared global variable to be declared as a thread local store variable.
  8. 8. The interrupt processing method of claim 5 wherein the CPU emulation module prohibits the reloading of the dynamic library.

Description

Interrupt processing method for CPU simulation Technical Field The invention relates to the technical field of chip simulation verification, in particular to an interrupt processing method for CPU simulation. Background In the chip design verification stage, CPU simulation (such as RISC-VCPU) is a core link for verifying hardware functions. In the CPU emulation verification scenario, the firmware program generally includes a main program that implements conventional service logic and an interrupt program that implements hardware interrupt response logic, both of which need to implement register read and write by invoking an operation task of the CPU emulation module. However, in the existing CPU emulation verification scenario, the main program and the interrupt program do not have explicit execution sequence control, which may simultaneously operate the same register, resulting in coverage of the configuration value, abnormal emulation logic, and risk of concurrency collision. Therefore, how to improve the reliability of the CPU simulation verification becomes a problem to be solved. Disclosure of Invention Aiming at the technical problems, the invention adopts the following technical scheme: an interrupt handling method for CPU emulation, the method comprising: S201, when the interrupt mark in the received target program is a first preset value, executing the target program, and setting an interrupt signal corresponding to a CPU simulation module to be a second preset level after the execution of the target program is completed; s202, when the received interrupt identifier in the target program is a second preset value, acquiring an interrupt program execution state of an interrupt signal corresponding to the CPU simulation module; s203, if the interrupt signal is that the execution state of the interrupt program of the first preset level meets the preset condition, executing the target program; s204, if the interrupt signal is the first preset level and the interrupt program execution state does not meet the preset condition, the target program is executed after waiting for the interrupt signal to change to the second preset level. Compared with the prior art, the interrupt processing method for CPU simulation has obvious beneficial effects, by means of the technical scheme, the interrupt processing method for CPU simulation can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following beneficial effects: Compared with the prior art, the invention adds the interrupt identifier in the target program, and the firmware program actively acquires the interrupt signal and sets the interrupt signal, thereby effectively avoiding the global variable address conflict caused by asynchronous execution of the program, increasing the execution state of the interrupt program, realizing the mechanism that the interrupt program is immediately executed according to the interrupt identifier and the interrupt program execution state signal, avoiding the simultaneous operation of the registers of the two types of programs by the main program, ensuring the atomicity of configuration logic, avoiding the concurrent conflict, conforming to the sequential logic with the interrupt response priority, and improving the simulation reliability. Drawings In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. FIG. 1 is a schematic flow chart of a CPU simulation acceleration system according to an embodiment of the present invention when a computer program is executed by a processor; fig. 2 is a flow chart of an interrupt processing method for CPU emulation according to a second embodiment of the present invention. Detailed Description The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention. Referring to fig. 1, a schematic architecture diagram of a CPU emulation acceleration system according to a first embodiment of the present invention is provided, where the system includes a verification platform, a CPU emulation module, and a dynamic library, where the CPU emulation module includes a call task, an operation task, and an operable register, and the dynamic library is obtained