CN-122019110-A - Chip calculation dynamic scheduling method based on proportional stress points

Abstract

The invention discloses a chip calculation power dynamic scheduling method based on proportional stress points, and relates to the technical field of chip calculation power optimization and integrated circuit control. According to the invention, the proportional reference model among the chip operation parameters is established, the operation data such as load, frequency, power consumption, temperature and the like are collected in real time, the proportional stress points affecting the stability of the system are identified, and the dynamic allocation and the scheduling of the calculation power resources are carried out based on the proportional stress points. When the operation proportion deviates from the safety interval, the multi-core calculation force is automatically migrated, limited in frequency, converged in load and the like, so that the chip always works in the optimal proportion interval. The invention can reduce power consumption fluctuation and performance jitter while ensuring the calculation efficiency, prolongs the service life of the chip, and is suitable for real-time calculation power scheduling of various general and special calculation chips such as CPU, GPU, NPU and the like.

Inventors

• Gui Wuyan

Assignees

• 珠海市工正科技有限公司

Dates

Publication Date

20260512

Application Date

20260405

Claims (5)

1. 1. A dynamic chip computing power dispatching method based on proportional stress points is characterized in that chip loads are normalized to [0,1] continuous proportional values, and self-adaptive adjustment of computing power resources is achieved according to stress points on a proportional interval.
2. 2. The method of claim 1, wherein the stress points comprise at least a low load stress point, an equilibrium stress point, a high load stress point three-level ratio threshold.
3. 3. The method of claim 1, wherein scheduling content includes calculating a core turn-on number, an operating frequency, an operating voltage, a data bandwidth, and a power consumption mode.
4. 4. The method of claim 1, wherein the force adjustment is smoothly continuous over the proportional interval without step jump.
5. 5. An artificial intelligence chip, characterized in that the dynamic dispatching method based on proportional stress points is adopted according to any one of claims 1-4.

Description

Chip calculation dynamic scheduling method based on proportional stress points 1. Technical field The invention relates to the technical fields of chip calculation power dispatching, integrated circuit control and artificial intelligence calculation power optimization, in particular to a chip calculation power dynamic dispatching method based on proportional stress points, which is suitable for load distribution, power consumption control and performance dispatching of various calculation chips such as CPU, GPU, NPU, ASIC. 2. Background art The current chip calculation power scheduling mostly adopts a fixed threshold value, a fixed priority or an average distribution mode, and the problems that 1, calculation power distribution is excessively concentrated to cause local overheating, power consumption surge or excessive dispersion to cause lower overall efficiency, 2, the accurate identification of key bottleneck nodes of a system is lacking, the scheduling action is delayed to load change and response is not timely, 3, the traditional algorithm aims at full load or fixed proportion, and the stability interval and critical stress points of the chip under different loads are not considered, so that performance jitter, power consumption runaway or life attenuation acceleration easily occurs. The prior art fails to identify system stress key points from the bottom layer proportion relation, and is difficult to realize dynamic optimal balance among performance, power consumption and stability. 3. Summary of the invention The invention provides a chip calculation power dynamic scheduling method based on a proportion philosophy and a stress point recognition principle, which establishes a proportion model among calculation power load, power consumption, temperature and bandwidth by collecting chip operation data in real time, positions proportion stress points and realizes dynamic, self-adaptive and low-jitter calculation power distribution. The method comprises the following core steps of 1, establishing a chip multi-dimensional operation parameter proportion reference model which comprises the proportion relation among parameters such as core quantity, frequency, load rate, temperature, power consumption, data throughput and the like, 2, collecting current operation parameters in real time, calculating deviation values of actual proportion and reference proportion, identifying proportion stress points which are key proportion nodes decisively influencing the stability and efficiency of the whole system, 3, dynamically distributing calculation force resources according to the types of the stress points, namely giving calculation force inclination to high-priority tasks, carrying out calculation force convergence on non-key tasks and avoiding overall proportion unbalance, 4, setting a safe proportion interval, automatically reducing frequency or limiting current when a scheduling action approaches to a critical proportion, preventing the unstable interval from entering, 5, periodically updating the proportion model, adapting to scenes such as chip aging, environmental temperature change, task type switching and the like, and keeping long-term optimal scheduling effect. The invention has the advantages that 1, proportional stress points are used as core dispatching basis, and the whole efficiency of the chip is obviously improved instead of simple average or full load operation, 2, the dynamic response load change reduces the power consumption waste and the performance fluctuation, and prolongs the stable working life of the chip, 3, the invention adapts to multi-core and heterogeneous chip architecture, can be widely applied to mobile terminals, server terminals, edge computing and AI reasoning chips, 4, the dispatching logic is light in weight, the computing cost is small, a large amount of extra computing force is not occupied, and the invention is suitable for hardware-level real-time dispatching. 4. Detailed description of the preferred embodiments 1. And (3) initializing on the chip, reading a preset proportion reference, and establishing an initial proportion model which comprises a normal working proportion interval, an early warning proportion interval and a critical stress proportion threshold value. 2. In the running process, the data of each core load, frequency, temperature and power consumption are collected every fixed time slice, and a real-time proportional vector is formed after normalization processing. 3. The system compares the real-time proportion vector with a reference model, calculates the deviation degree, and positions the current stress point, namely, if the proportion of a certain core load is too high, the stress point is judged to be a stress concentration type stress point, if the proportion of the whole power consumption exceeds a threshold value, the stress point is judged to be an overrun type stress point, and if the temperature rising rate is not matched with the load proportion