CN-122019151-A - Interrupt and exception cooperative processing method suitable for supporting RISC-V vector expansion processor

CN122019151ACN 122019151 ACN122019151 ACN 122019151ACN-122019151-A

Abstract

The invention discloses an interrupt and exception collaborative processing method suitable for supporting a RISC-V vector expansion processor, wherein exception processing comprises the steps of providing an exception detection module in a VPU and a CPU, respectively used for dynamically monitoring various exception events during instruction execution, feeding back to the CPU along with instructions, judging the exception of the marked instructions, uniformly processing the exception events in the stage of instruction entering and submitting, carrying out grading calibration by the CPU after receiving an interrupt request, suspending the interrupt request if the interrupt request is calibrated to be low interrupt grade, immediately starting an interrupt processing flow if the interrupt request is calibrated to be high interrupt grade, and carrying out exception and interrupt concurrent processing, when the CPU receives the interrupt request calibrated to be high grade, immediately starting the interrupt processing flow, suspending the interrupt request and preferentially processing the exception events. The invention realizes light, accurate and efficient exception and interrupt management through decoupling cooperation of the CPU and the vector processing unit, and is suitable for low-overhead system control under a high concurrent vector operation scene.

Inventors

ZHANG XIRAN
LI DONGSHENG
WU YE

Assignees

南京英麒智能科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260120

Claims (9)

1. The interrupt and exception cooperative processing method is applicable to supporting RISC-V vector expansion processors, and is applied to a system structure of cooperation and decoupling of a CPU and a VPU under a RISC-V architecture, and is characterized by comprising exception processing, interrupt processing and exception and interrupt concurrent processing, wherein the exception processing comprises the steps that an exception detection module is arranged in the VPU and the CPU, the exception detection module in the VPU is used for dynamically monitoring various exception events during instruction execution and marking and feeding back to the CPU along with the instruction, and the exception detection module in the CPU is used for judging the exception marked with the instruction and uniformly processing the exception events in the stage of entering and submitting the instruction; The interrupt processing comprises the steps that after receiving an interrupt request, a CPU (central processing unit) carries out grading calibration according to interrupt types, if the interrupt request is calibrated to be of a low interrupt level, the CPU suspends the interrupt request, and if the interrupt request is calibrated to be of a high interrupt level, the CPU immediately starts an interrupt processing flow; The concurrent processing of the exception and the interrupt comprises the steps of immediately starting an interrupt processing flow no matter whether an exception event exists currently or not when the CPU receives an interrupt request marked as high-level, suspending the interrupt request when the CPU receives the interrupt request marked as ground level, and preferentially processing the exception event.
2. The interrupt and exception co-processing method of claim 1, wherein, during said exception handling, when there are a plurality of instructions carrying exception flags entering the commit phase, the CPU processes the earliest instruction carrying an exception flag in the commit queue.
3. The interrupt and exception cooperative processing method according to claim 1, wherein after the exception detection module in the CPU determines the exception, the CPU triggers a unified pipeline cleaning mechanism, stops transmitting new instructions to the VPU, flushes the instructions that are not submitted in the VPU, empties the non-submitted instructions in the front end of the CPU and the execution queue, retains field information corresponding to the exception instructions, jumps to the RISC-V standard exception handling entry, and executes a subsequent exception handling flow.
4. The interrupt and exception co-processing method of claim 1, wherein during said interrupt processing, for interrupt requests of low interrupt level, the CPU temporarily stores an interrupt signal to a wait register in the interrupt processing module to be in a suspended state, and when it is confirmed that the VPU instruction commit queue is empty, the CPU issues an "interrupt start processing" signal to the interrupt processing module, thereby starting a subsequent processing flow of suspending the interrupt.
5. The interrupt and exception co-processing method of claim 1, wherein during said interrupt processing, for interrupt requests of high interrupt level, the CPU immediately suspends instruction issue to the VPU and discards all issued but not yet committed vector instruction execution results, directly starting interrupt processing flow.
6. The interrupt and exception co-processing method of claim 5, wherein during said interrupt processing, the CPU saves context information corresponding to an earliest instruction waiting to commit in the commit queue as a minimum recovery point for an interrupt scene.
7. The interrupt and exception co-processing method according to claim 1, wherein in the exception and interrupt concurrent processing, when the CPU receives an interrupt request number calibrated to be high-level, the CPU immediately starts the interrupt processing flow, and at the same time, the CPU immediately stops transmitting a new instruction to the VPU and clears an execution instruction which has not yet been submitted inside the VPU, and the CPU no longer accepts a commit from the VPU.
8. The interrupt and exception co-processing method of claim 1, wherein in the exception and interrupt concurrent processing, when the CPU receives an interrupt request number that is rated as ground, suspending the interrupt while allowing vector instructions that have been issued within the VPU to continue execution until all commit is completed.
9. The interrupt and exception co-processing method according to claim 1, wherein in the exception and interrupt concurrent processing, when the CPU receives an interrupt request number calibrated to a ground level, the CPU preferentially processes the exception, resumes the response to the suspended interrupt, and enters an interrupt service flow.

Description

Interrupt and exception cooperative processing method suitable for supporting RISC-V vector expansion processor Technical Field The invention relates to the technical field of general processors, in particular to an interrupt and exception collaborative processing method suitable for supporting a RISC-V vector expansion processor. Background RISC-V is an open source, modular instruction set architecture, and its vector expansion (RISC-V Vector Extension, RVV) provides great flexibility for integrating high-performance computing units, especially in superscalar microarchitectural designs, with great attention and research. With the introduction of RISC-V vector expansion, the processor obtains powerful capability for data-level parallel computing, and is particularly suitable for the high-performance computing fields of artificial intelligent reasoning, image processing, scientific computing and the like. To accommodate this trend, more and more processor architectures integrate vector processing units (Vector Processing Unit, VPUs) to achieve high throughput vector computing support. However, when vector processing logic is introduced, the original mechanism suffers from the following prominent drawbacks: With large resource consumption and rising hardware complexity, vector instructions typically involve large numbers of sub-operations with significantly higher granularity of execution and state management than scalar instructions. In order to support accurate exception handling for these sub-operations, a conventional reserve Reorder Buffer (ROB) needs to expand capacity, and introduces more state tracking and exception marking logic, which significantly increases hardware area and power consumption, resulting in an increase in implementation complexity. The execution time sequence is complex, and the accurate exception handling is difficult, namely in an out-of-order processor with superscalar instructions, out-of-order emission and out-of-order submission of instructions bring time sequence control challenges, and after VPU is introduced, the decoupling execution model and the multi-cycle instruction characteristics further disturb the submission boundary, so that the consistency of the instruction submission sequence and the exception accuracy are ensured to become extremely complex. The traditional method often needs to add an additional control path, prolongs the time sequence of a critical path, and influences the overall execution performance. Resource reclamation is blocked, throughput is affected, and corresponding resources (such as execution units, registers and state queues) are difficult to release in time due to long duration of vector operation. If the interrupt cannot be processed in an intervening manner in a reasonable time, not only the key hardware resources are occupied, but also the emission of subsequent instructions can be blocked, and the overall throughput rate and the system response elasticity are severely limited. The interrupt processing strategy lacking vector perception is that the traditional interrupt mechanism mainly relies on the ROB submitting state of a scalar path to judge interrupt time, and lacks perception capability on the execution state of the VPU. Under the condition that the VPU is not completed, the interrupt is made in the trade response, which may cause the uncommon status not to be submitted, the data is inconsistent or the abnormal incomplete processing, and the correctness of the program semantics is affected. Vector exception handling paths are unclear, debugging and verification are difficult, unified architecture specifications are not available in current vector exception handling, and a standardized exception reporting mechanism and a standardized state query interface are lacked in the internal execution process of the VPU, so that a developer is difficult to locate an exception source in the debugging process, the exception handling flow is opaque, the verification and test cost is high, and the industrial-level stability requirement is difficult to meet. Disclosure of Invention The invention aims to provide an interrupt and exception cooperative processing method suitable for supporting a RISC-V vector expansion processor, which realizes light, accurate and efficient exception and interrupt management through decoupling cooperation of a CPU and a vector processing unit and is suitable for low-overhead system control under a high concurrent vector operation scene. In order to achieve the above purpose, the interrupt and exception cooperative processing method suitable for supporting a RISC-V vector expansion processor is applied to a system structure of cooperation and decoupling of a CPU and a VPU under a RISC-V architecture, and comprises exception handling, interrupt handling and exception and interrupt concurrent processing, wherein the exception handling comprises the steps of providing an exception detection module in the VPU and the CPU, w