CN-122019246-A - Signal verification method, circuit and memory

Abstract

The disclosure relates to the field of integrated circuits and discloses a signal verification method, a circuit and a memory. The signal checking method comprises the steps of encoding a signal to be checked to obtain an encoded command, carrying out pipelined parity check on the encoded command to meet parity check delay, and decoding the encoded command to obtain the signal to be checked.

Inventors

• Jin Xiujin

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260512

Application Date

20241108

Claims (11)

1. 1. A signal verification method, the signal verification method comprising: encoding the signal to be checked to obtain an encoding command; pipelining the encoded commands to parity satisfy a parity delay; and decoding the coded command to obtain the signal to be verified.
2. 2. The signal verification method according to claim 1, wherein said pipelining the parity for the encoded command comprises: Registering each bit of data in the coding command respectively; and pipelining the encoded command based on the parity delay.
3. 3. The signal verification method of claim 1, wherein, The signal to be checked comprises a command address signal; The parity delay corresponding to the command address signal is registered in the mode register MR 5.
4. 4. The signal verification method of claim 1, wherein, The data bit number of the coding command is n, wherein n is greater than or equal to 1; The sum of the data bit numbers of the signals to be verified is more than 2 n-1 and less than or equal to 2 n .
5. 5. A signal verification circuit, the signal verification circuit comprising: The command encoder is configured to encode the signal to be verified to obtain an encoded command; a parity pipeline coupled to the command encoder, configured to pipeline parity of the encoded command, satisfying a parity delay; And the command decoder is coupled with the parity check pipeline and is configured to decode the coded command to obtain the signal to be checked.
6. 6. The signal verification circuit of claim 5, wherein, The parity pipeline is further configured to register each bit of data in the encoded command separately, and pipeline the encoded command for parity based on the parity delay.
7. 7. The signal verification circuit of claim 5, wherein, The number of storage elements in the parity pipeline is determined based on the number of data bits of the encoded command and the parity delay.
8. 8. The signal verification circuit of claim 5, wherein, The signal to be checked comprises a command address signal; The parity delay corresponding to the command address signal is registered in the mode register MR 5.
9. 9. The signal verification circuit of claim 5, wherein, The data bit number of the coding command is n, wherein n is greater than or equal to 1; The sum of the data bit numbers of the signals to be verified is more than 2 n-1 and less than or equal to 2 n .
10. 10. A memory, characterized in that the memory comprises a signal verification circuit as claimed in any one of claims 5 to 9.
11. 11. The memory of claim 10, wherein the memory comprises at least dynamic random access memory, DRAM.

Description

Signal verification method, circuit and memory Technical Field The present disclosure relates to the field of integrated circuits, and in particular, to a signal verification method, circuit and memory. Background DRAM (Dynamic Random Access Memory ) is a semiconductor memory whose main principle of operation is to use the charge in the memory cells to characterize the stored data, i.e. whether a binary bit (bit) is a 1 or a 0. DDR (double Rate synchronous dynamic random Access memory) is a DRAM with double data transfer rate, which is twice the system clock frequency, and its transfer performance is superior to that of conventional DRAM due to the increase in speed. DDR supports both Parity (Parity) and Cyclic Redundancy Check (CRC) data checking methods. Among them, parity check is one of the simplest check methods, and its check code has only one bit. Parity checks check the data code and the parity of the total number of data "1" s in the check code to determine whether the data code is correct. Parity works on the principle that if an error occurs, such as a flip of one or more bits, during transmission or storage, the originally retained parity is destroyed. Therefore, by counting the number of "1" s in the received data at the receiving end and comparing with the expected parity, the occurrence of an error can be detected. If the counted number of "1's" does not match the expected number, i.e., the actual number does not match the expected number, then it may be determined that an error occurred during transmission or storage. In DDR, pipelined parity is employed, and at the same time, the specification of parity latency needs to be satisfied. However, in the prior art, pipeline circuits for parity check have room for further optimization. Disclosure of Invention In view of this, embodiments of the present disclosure provide a signal checking circuit and a memory, which can reduce the number of data bits that need to be checked, and reduce the number of storage elements in a parity pipeline. The technical scheme of the embodiment of the disclosure is realized as follows: The embodiment of the disclosure provides a signal verification method, which comprises the steps of encoding a signal to be verified to obtain an encoded command, carrying out pipelined parity check on the encoded command to meet parity check delay, and decoding the encoded command to obtain the signal to be verified. In some embodiments of the present disclosure, the pipelining of the encoded commands includes separately registering each bit of data in the encoded commands, pipelining of the encoded commands based on the parity delays. In some embodiments of the present disclosure, the signal to be verified includes a command address signal, and the parity delay corresponding to the command address signal is registered in a mode register MR 5. In some embodiments of the present disclosure, the number of data bits of the encoded command is n, n is greater than or equal to 1, and the sum of the number of data bits of the signal to be verified is greater than 2 n-1 and less than or equal to 2 n. The embodiment of the disclosure also provides a signal checking circuit, which comprises a command encoder configured to encode a signal to be checked to obtain an encoded command, a parity check pipeline coupled to the command encoder and configured to perform pipelined parity check on the encoded command to meet parity check delay, and a command decoder coupled to the parity check pipeline and configured to decode the encoded command to obtain the signal to be checked. In some embodiments of the present disclosure, the parity pipeline is further configured to register each bit of data in the encoded command separately, and pipeline the encoded command for parity based on the parity delay. In some embodiments of the present disclosure, the number of storage elements in the parity pipeline is determined based on the number of data bits of the encoded command and the parity delay. In some embodiments of the present disclosure, the signal to be verified includes a command address signal, and the parity delay corresponding to the command address signal is registered in a mode register MR 5. In some embodiments of the present disclosure, the number of data bits of the encoded command is n, n is greater than or equal to 1, and the sum of the number of data bits of the signal to be verified is greater than 2 n-1 and less than or equal to 2 n. The embodiment of the disclosure also provides a memory, which comprises the signal checking circuit in the scheme. In some embodiments of the present disclosure, the memory comprises at least dynamic random access memory, DRAM. It can be understood that the signal to be checked is encoded first to obtain the encoded command, and then the encoded command is pipelined to perform parity check, so that the number of data bits required to be checked is reduced, and thus, the number of storage elements in the parit