CN-122019247-A - Error correction capability adaptation method, device and storage medium

CN122019247ACN 122019247 ACN122019247 ACN 122019247ACN-122019247-A

Abstract

The application discloses an adaptation method, equipment and a storage medium of error correction capability, which comprise the steps of responding to an error correction capability adaptation instruction, acquiring an address offset parameter of a storage body based on the error correction capability adaptation instruction, reading a plurality of data blocks in the storage body according to the address offset parameter, determining error data exceeding the capacity of a single error correction processing unit in the plurality of data blocks, dividing the error data into a plurality of error subsets according to the mapping relation between the physical distribution characteristics of the error data and a logic address, distributing the error subsets to the plurality of error correction processing units for parallel error correction decoding, judging whether the error data is successfully corrected according to the decoding result of each error correction processing unit, and setting the address offset parameter as address offset configuration for performing read-write operation on similar data if the error correction is successful. The application realizes the technical effects of improving the error correction success rate and the system adaptation capability by sensing the physical distribution of errors and intelligent segmentation parallel processing.

Inventors

HUANG LINYONG
LIN YIN
WU JIAN
DUAN HUIHE

Assignees

得一微电子股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260109

Claims (10)

1. A method of adapting error correction capability, the method comprising the steps of: responding to an error correction capability adaptation instruction, and acquiring an address offset parameter of a storage body based on the error correction capability adaptation instruction; Reading a plurality of data blocks in a memory bank according to the address offset parameter; determining error data exceeding the capacity of a single error correction processing unit in the plurality of data blocks; dividing the error data into a plurality of error subsets according to the mapping relation between the physical distribution characteristics of the error data and the logical addresses, and distributing the error subsets to a plurality of error correction processing units for parallel error correction decoding; judging whether the error data is successfully corrected according to the decoding result of each error correction processing unit; If the error correction is successful, setting the address offset parameter as the address offset configuration for performing read-write operation on the same kind of data.
2. The method of adapting error correction capability according to claim 1, wherein the step of responding to the error correction capability adaptation instruction and acquiring the address offset parameter of the memory bank based on the error correction capability adaptation instruction further comprises: Responding to a target data writing instruction and determining the data length of the target data; Calculating a difference value between the data length and a preset error correction data length, and generating an initial address offset parameter based on the difference value; According to the initial address offset parameter, adjusting the initial write address of the target data in the memory bank; And writing the target data into the memory bank according to the adjusted initial writing address.
3. The method of adapting error correction capability according to claim 2, wherein the step of adjusting a starting write address of the target data in the memory bank according to the initial address offset parameter comprises: Acquiring the historical error correction success rate of the memory bank and the current working state performance parameters; Calculating a weighted evaluation value based on the historical error correction success rate and the current working state performance parameter, and dynamically optimizing the initial address offset parameter based on the weighted evaluation value to obtain an optimized address offset parameter; and determining the initial write address of the target data according to the optimized address offset parameter.
4. The method of adapting error correction capability according to claim 2, wherein the step of writing the target data to the memory bank at the adjusted start write address comprises: splitting the target data into a plurality of consecutive data segments; generating an address offset sequence according to the address offset parameter; Determining the initial writing address of each data segment in sequence according to the address offset sequence; And writing each data segment into the memory bank according to the determined initial writing address.
5. The method of adapting error correction capability according to claim 4, wherein the step of writing each of said data segments into said memory bank at said determined start write address comprises: calculating an end address based on a start write address of the data segment and a data segment length, and determining whether the start write address and the end address are both within an effective addressing range of the memory bank; If yes, continuing to write the data segment based on the initial write address; If not, interrupting the writing process, recording address boundary crossing information, and executing a preset address boundary crossing processing strategy, wherein the preset address boundary crossing processing strategy comprises address correction or error report generation operation.
6. The method for adapting error correction capability according to claim 1, wherein the step of dividing the error data into a plurality of error subsets according to the mapping relation between the physical distribution characteristics of the error data and the logical addresses and distributing the plurality of error subsets to a plurality of error correction processing units for parallel error correction decoding comprises: analyzing an error mode and distribution characteristics of the error data; dividing the error data into a plurality of error subsets according to the distribution characteristics; And polling the real-time load rate of each error correction processing unit, and distributing each error subset to the error correction processing units with the real-time load rate smaller than a first load threshold value for parallel processing.
7. The method of adapting error correction capability according to claim 6, wherein the step of polling a real-time load rate of each of the error correction processing units, and assigning each of the error subsets to the error correction processing units having the real-time load rate less than a first threshold value for parallel processing comprises: monitoring the processing progress of each error correction processing unit on the distributed error subsets; And if the processing progress of the error correction processing unit is monitored to be smaller than a preset progress threshold value or the real-time load rate is larger than a second load threshold value, the error subset which is not decoded and completed by the error correction processing unit is redistributed to the error correction processing unit with the lowest current load rate, wherein the second load threshold value is larger than or equal to the first load threshold value.
8. The method for adapting error correction capability according to claim 1, wherein the method for adapting error correction capability further comprises: monitoring error correction performance indexes of similar data subjected to read-write operation by adopting the address offset parameters; triggering a recalculation and adaptation process of the address offset parameters for the same kind of data when the error correction performance index is lower than a preset performance threshold in a plurality of continuous operation periods; And updating the read-write operation offset configuration of the same kind of data by adopting the recalculated address offset parameters.
9. An adaptation device of error correction capability, characterized in that the adaptation device of error correction capability stores a computer program which, when executed by a processor, implements the adaptation method of error correction capability of any of claims 1-8.
10. A storage medium storing a computer program which, when executed by a processor, implements the method of adapting error correction capability of any one of claims 1-8.

Description

Error correction capability adaptation method, device and storage medium Technical Field The present application relates to the field of data error correction technologies of storage devices, and in particular, to an adaptation method, an apparatus, and a storage medium for error correction capability. Background In a NAND flash memory based storage device, a main controller ensures data reliability through error correction codes (e.g., BCH codes, LDPC codes). The error correction process is typically performed in units of data units of a fixed length (e.g., 1KB DMA region). However, the physical Page (Page) length (e.g., 18,368 bytes) of the flash memory chip is fixed, while the parity area length required to host to match different error correction levels (different ECC matrices) may vary. When the effective data length of a physical page is not divisible by the length of the error correction processing unit, the end of the page creates a "residual data area" that is not covered by any complete error correction unit. In the case of subsequent reading, the residual data area will collectively represent an error data burst exceeding the capacity of a single error correction processing unit (e.g., a decoding unit corresponding to a DMA), if an error occurs. The conventional solution is to use an "address offset" programming and reading technique, which causes the residual data to be written in a scattered manner to the tail of a plurality of consecutive data blocks (DMAs) by sequentially advancing the column addresses during programming. In reading and error correction, the errors originally concentrated are distributed to a plurality of error correction processing units. However, the error data "scatter" strategy resulting from this solution is typically mechanical, average, or based on simple address offset calculations only, and completely ignores the actual physical distribution characteristics of the error data in the storage medium, as well as the complex mapping between these physical distributions and logical addresses. The physical characteristics of flash memory cells (e.g., process variations, erase wear, adjacent cell disturb) result in a distribution of errors that is not entirely uniform or random, often with spatial correlation. Simple average dispersion may split error bits with strong correlation into different error correction units, destroying the inherent cluster characteristics of the errors, but rather exceeding the error correction capability of each unit for random errors, or failing to effectively split according to the actual physical cluster of errors, resulting in some error correction units still being allocated to excessive associated errors and failing to decode. In addition, different address mapping strategies (such as wear leveling and remapping introduced by bad block management) enable the corresponding relation between the logical address and the physical unit to be dynamically changed, so that the unpredictability of error distribution is further increased. The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present application and is not intended to represent an admission that the foregoing is prior art. Disclosure of Invention The application mainly aims to provide an adaptation method, equipment and a storage medium of error correction capability, and aims to solve the technical problem that error correction efficiency is low due to neglecting of error physical distribution and address mapping in the existing error correction method. In order to achieve the above object, the present application provides a method for adapting error correction capability, the method comprising: responding to an error correction capability adaptation instruction, and acquiring an address offset parameter of a storage body based on the error correction capability adaptation instruction; Reading a plurality of data blocks in a memory bank according to the address offset parameter; determining error data exceeding the capacity of a single error correction processing unit in the plurality of data blocks; dividing the error data into a plurality of error subsets according to the mapping relation between the physical distribution characteristics of the error data and the logical addresses, and distributing the error subsets to a plurality of error correction processing units for parallel error correction decoding; judging whether the error data is successfully corrected according to the decoding result of each error correction processing unit; If the error correction is successful, setting the address offset parameter as the address offset configuration for performing read-write operation on the same kind of data. In an embodiment, before the step of responding to the error correction capability adapting instruction and acquiring the address offset parameter of the memory bank based on the error correction capability adapting instruc