CN-122019248-A - Memory management method, memory storage device and memory control circuit unit

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The memory management method includes forming a first codeword from first dummy data and first data read from a rewritable nonvolatile memory module, performing a first decoding operation according to the first dummy data to update the first dummy data to obtain second dummy data, forming a second codeword from the first data and the second dummy data, and performing a second decoding operation according to the second codeword.

Inventors

• LIN YUXIANG
• HUANG BAILUN

Assignees

• 群联电子股份有限公司

Dates

Publication Date

20260512

Application Date

20260130

Claims (20)

1. 1. A memory management method for a rewritable non-volatile memory module, the memory management method comprising: Forming a first codeword from first dummy data and first data read from the rewritable non-volatile memory module; Performing a first decoding operation according to the first virtual data to update the first virtual data, thereby obtaining second virtual data; Forming the first data and the second virtual data into a second codeword, and And executing a second decoding operation according to the second code word.
2. 2. The memory management method according to claim 1, wherein the first data is composed of write data and parity data, and the write data or a part of data in the parity data has been deleted.
3. 3. The memory management method according to claim 2, wherein the first virtual data is used as the partial data.
4. 4. The memory management method of claim 2, further comprising: Performing an encoding operation on the write data to generate the parity data; And deleting the part of the writing data or the parity data, and storing the writing data and the parity data deleted by the part of the writing data or the parity data deleted by the part of the writing data and the writing data into the rewritable nonvolatile memory module.
5. 5. The memory management method of claim 2, further comprising: In response to the parity data being deleted the partial data, composing an error correction code with the first dummy data, and performing the first decoding operation on the first dummy data using the error correction code.
6. 6. The memory management method of claim 2, further comprising: And in response to the write data being deleted the partial data, taking the parity data as an error correction code and performing the first decoding operation on the first dummy data using the error correction code.
7. 7. The memory management method of claim 1, wherein the first decoding operation uses the same parity check matrix as the second decoding operation.
8. 8. The memory management method according to claim 1, wherein the logarithmic likelihood ratio corresponding to the first virtual data is zero.
9. 9. The memory management method of claim 1, wherein an absolute value of a log likelihood ratio corresponding to the second virtual data is greater than an absolute value of a log likelihood ratio corresponding to the first virtual data.
10. 10. The memory management method of claim 1, wherein the decoding algorithm corresponding to the first decoding operation is different from the decoding algorithm corresponding to the second decoding operation.
11. 11. The memory management method of claim 1, wherein the first decoding operation is a bit flip decoding operation.
12. 12. The memory management method of claim 11, further comprising: In the bit flip decoding operation, a value of a bit in the first dummy data is flipped in response to a number of non-zero syndromes associated with the bit being greater than a preset threshold.
13. 13. The memory management method of claim 1, wherein the second decoding operation is a low density parity check decoding operation.
14. 14. A memory storage device, comprising: a connection interface unit connected to the host system; rewritable nonvolatile memory module, and A memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module, Wherein the memory control circuit unit is configured to: The first dummy data and the first data read from the rewritable non-volatile memory module are combined into a first codeword, Performing a first decoding operation based on the first dummy data to update the first dummy data to obtain second dummy data, The first data and the second dummy data are formed into a second codeword, And executing a second decoding operation according to the second code word.
15. 15. The memory storage device of claim 14, wherein the first data consists of write data and parity data, and a portion of the write data or the parity data has been deleted.
16. 16. The memory storage device of claim 15, wherein the first virtual data is used as the partial data.
17. 17. The memory storage device of claim 15, wherein the memory control circuit unit is further to: Performing an encoding operation on the write data to generate the parity data; And deleting the part of the writing data or the parity data, and storing the writing data and the parity data deleted by the part of the writing data or the parity data deleted by the part of the writing data and the writing data into the rewritable nonvolatile memory module.
18. 18. The memory storage device of claim 15, wherein the memory control circuit unit is further to: In response to the parity data being deleted the partial data, composing an error correction code with the first dummy data, and performing the first decoding operation on the first dummy data using the error correction code.
19. 19. The memory storage device of claim 15, wherein the memory control circuit unit is further to: And in response to the write data being deleted the partial data, taking the parity data as an error correction code and performing the first decoding operation on the first dummy data using the error correction code.
20. 20. The memory storage device of claim 14, wherein the first decoding operation uses the same parity check matrix as the second decoding operation.

Description

Memory management method, memory storage device and memory control circuit unit Technical Field The present invention relates to a memory management technology, and more particularly, to a memory management method, a memory storage device, and a memory control circuit unit. Background Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable nonvolatile memory module (e.g., flash memory) has characteristics of nonvolatile data, power saving, small size, and no mechanical structure, it is very suitable for being built in the various portable electronic devices as exemplified above. In order to maintain the reliability of the data, the data is encoded to generate the corresponding error correction code before storing the data in the rewritable nonvolatile memory module. The ECC is then stored in the rewritable nonvolatile memory module along with the corresponding data. In some cases, in order to correspond to the actual writable length, the error correction code (or data) is deleted and then stored in the rewritable nonvolatile memory module. Then, when the data and the error correction code are read out from the rewritable nonvolatile memory module, the virtual data can be added to complement the data length of the deleted error correction code (or data), so that the virtual data, the data read out from the rewritable nonvolatile memory module and the error correction code can form a complete codeword. Generally, in conventional iterative decoding operations, each iterative operation is performed based on a complete codeword. However, the error in the virtual data is difficult to converge, which results in problems of increased iteration number and low decoding efficiency. Disclosure of Invention The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can improve decoding speed. An exemplary embodiment of the present invention provides a memory management method for a rewritable nonvolatile memory module, and the memory management method includes composing first dummy data and first data read from the rewritable nonvolatile memory module into a first codeword, performing a first decoding operation according to the first dummy data to update the first dummy data to obtain second dummy data, composing the first data and the second dummy data into a second codeword, and performing a second decoding operation according to the second codeword. In an example embodiment of the present invention, the first data is composed of write data and parity data, and a part of the write data or the parity data has been deleted. In an exemplary embodiment of the present invention, the first dummy data is used as partial data. In an exemplary embodiment of the invention, the memory management method further includes performing an encoding operation on the write data to generate parity data, deleting a portion of the write data or the parity data, and storing the write data and the parity data of the deleted portion of the data or the parity data and the write data of the deleted portion of the data in the rewritable nonvolatile memory module. In an example embodiment of the present invention, performing a first decoding operation according to first dummy data includes, in response to the parity data being deleted of the partial data, composing an error correction code with the parity data of the deleted partial data and the first dummy data, and performing the first decoding operation on the first dummy data using the error correction code. In an example embodiment of the present invention, performing the first decoding operation according to the first dummy data includes deleting a portion of the data in response to the write data, using the parity data as an error correction code, and performing the first decoding operation on the first dummy data using the error correction code. In an example embodiment of the present invention, the first decoding operation and the second decoding operation use the same parity check matrix. In an exemplary embodiment of the present invention, the log likelihood ratio (Log Likelihood Ratio, LLR) corresponding to the first dummy data is zero. In an exemplary embodiment of the present invention, the absolute value of the log likelihood ratio corresponding to the second virtual data is greater than the absolute value of the log likelihood ratio corresponding to the first virtual data. In an exemplary embodiment of the present invention, the decoding algorithm corresponding to the first decoding operation is different from the decoding algorithm corresponding to the second decoding operation. In an example embodiment of the present invention, the first decoding operation is a bit flipping (bit flipping) decoding operation. In an example embodiment of the present invention, the memory management meth