CN-122019256-A - Dual-CPU arbitration reset system and control method thereof

Abstract

The invention relates to the technical field of CPU arbitration reset, in particular to a dual CPU arbitration reset system and a control method thereof, which ensure independent control of power supply of two CPUs and avoid mutual interference during reset operation by arranging a first controlled power supply and a second controlled power supply which are mutually independent and respectively supply power to the first CPU and the second CPU; the second CPU controls the first controlled power supply through the first power supply control circuit, the first CPU controls the second controlled power supply through the second power supply control circuit, accurate control of the normal CPU on the fault CPU power supply is achieved, the bidirectional heartbeat communication link between the first CPU and the second CPU can monitor the running state mutually in real time and reliably, a direct basis is provided for fault judgment, the whole framework achieves effective arbitration and reset triggering during double-CPU system faults through cooperation of the modules, and reliability and independence of system fault recovery are improved.

Inventors

• LIN XIAOLING
• LIN TONGYI

Assignees

• 福建师范大学协和学院

Dates

Publication Date

20260512

Application Date

20260127

Claims (10)

1. 1. The double-CPU arbitration reset system is characterized by comprising a first controlled power supply, a second controlled power supply, a first CPU, a second CPU, a first power supply control circuit and a second power supply control circuit; The input end of the first controlled power supply and the input end of the second controlled power supply are connected with an external main power supply; the output end of the first controlled power supply is connected with the power supply end of the first CPU, and the power supply enabling end of the first controlled power supply is connected with the general input and output end of the second CPU through the second power supply control circuit; The output end of the second controlled power supply is connected with the power supply end of the second CPU, and the power supply enabling end of the second controlled power supply is connected with the general input and output end of the first CPU through the first power supply control circuit; and a bidirectional heartbeat communication link used for mutually monitoring the running state is arranged between the first CPU and the second CPU.
2. 2. The dual CPU arbitration reset system of claim 1, wherein the first power control circuit includes a resistor R1 and a capacitor C1, one end of the resistor R1 is connected to the general input/output terminal of the first CPU, the other end of the resistor R1 is connected to one end of the capacitor C1 and the power enable terminal of the second controlled power supply, respectively, and the other end of the capacitor C1 is grounded.
3. 3. The dual CPU arbitration reset system of claim 2, wherein the first power control circuit further includes a resistor R2, one end of the resistor R2 is respectively connected to a power enable end of the second controlled power supply, one end of a capacitor C1, and the other end of the resistor R2 is grounded.
4. 4. The dual CPU arbitration reset system of claim 2, wherein the first power control circuit further comprises a diode D1, wherein an anode of the diode D1 is connected to the general purpose input/output terminal of the first CPU through a resistor R1, and a cathode of the diode D1 is connected to one terminal of a capacitor C1 and a power enable terminal of the second controlled power supply, respectively.
5. 5. The dual CPU arbitration reset system of claim 1, wherein the second power control circuit includes a resistor R3 and a capacitor C2, one end of the resistor R3 is connected to the general input/output terminal of the second CPU, the other end of the resistor R3 is connected to one end of the capacitor C2 and the power enable terminal of the first controlled power supply, respectively, and the other end of the capacitor C2 is grounded.
6. 6. The dual CPU arbitration reset system of claim 5, wherein the second power control circuit further includes a resistor R4, one end of the resistor R4 is respectively connected to a power enable end of the first controlled power supply, one end of a capacitor C2, and the other end of the resistor R3, and the other end of the resistor R4 is grounded.
7. 7. The dual CPU arbitration reset system of claim 5, wherein the second power control circuit further includes a diode D2, an anode of the diode D2 is connected to a general purpose input/output terminal of the second CPU through a resistor R3, and a cathode of the diode D2 is connected to one terminal of a capacitor C2 and a power enable terminal of the first controlled power supply, respectively.
8. 8. A control method based on the dual CPU arbitration reset system of claim 1, comprising the steps of: s1, controlling the general input and output end of the first CPU to initialize to a high-resistance state, and controlling the general input and output end of the second CPU to initialize to the high-resistance state; s2, the first CPU and the second CPU monitor the running state through a bidirectional heartbeat communication link; If the first CPU judges that the second CPU fails, the first CPU executes a first reset arbitration operation on the second controlled power supply through a first power supply control circuit; And if the second CPU judges that the first CPU fails, the second CPU executes a second reset arbitration operation on the first controlled power supply through a second power supply control circuit.
9. 9. The method for controlling a dual CPU arbitration reset system according to claim 8, wherein in step S2, the first CPU performs a first reset arbitration operation on a second controlled power supply through a first power supply control circuit, specifically comprising: controlling the general input and output end of the first CPU to switch from a high-resistance state to an output mode and outputting a first control level; Transmitting the first control level to a power supply enabling end of a second controlled power supply through a first power supply control circuit, and increasing the voltage of the power supply enabling end of the second controlled power supply to be above a closing threshold value of the second controlled power supply; And after the general input/output end of the first CPU maintains the first control level for a preset period of time, the general input/output end of the first CPU is recovered to a high-resistance state, and the voltage of the power supply enabling end of the second controlled power supply is reduced to be below the starting threshold value of the second controlled power supply.
10. 10. The method for controlling a dual CPU arbitration reset system according to claim 8, wherein in step S2, the second CPU performs a second reset arbitration operation on the first controlled power supply through a second power supply control circuit, specifically comprising: Controlling the general input and output end of the second CPU to switch from a high-resistance state to an output mode and outputting a second control level; Transmitting the second control level to a power supply enabling end of a first controlled power supply through a second power supply control circuit, and increasing the voltage of the power supply enabling end of the first controlled power supply to be above a closing threshold value of the first controlled power supply; And after the general input/output end of the second CPU maintains the second control level for a preset period of time, the general input/output end of the second CPU is restored to a high-resistance state, and the voltage of the power supply enabling end of the first controlled power supply is reduced to be below the starting threshold value of the first controlled power supply.

Description

Dual-CPU arbitration reset system and control method thereof Technical Field The invention relates to the technical field of CPU arbitration reset, in particular to a dual-CPU arbitration reset system and a control method thereof. Background In electronic systems with high reliability requirements, dual CPU (or dual core) architectures are widely used, which guarantee stable operation of the system through redundant design and mutual monitoring. When one of the CPUs is halted due to program run-out, hardware abnormality and the like, the CPU which normally works needs to reset the fault CPU in time so as to quickly recover the whole function of the system. Traditional reset methods rely mainly on watchdog circuits or direct control of the reset pins of the faulty CPU. However, the watchdog circuit itself may fail due to hardware failure and cannot reliably send out a reset signal, and the soft reset mode of directly controlling the reset pin is difficult to thoroughly clear the abnormal latch state of the internal registers and part of peripheral devices of the CPU, so that the system may still be in an abnormal working state after reset, and the severe requirements of the high-reliability system on failure recovery cannot be met. Thus, there is a need for a dual CPU arbitration reset scheme that is more thorough in reset and reliable in control. Disclosure of Invention The invention aims to solve the technical problem of providing a double CPU arbitration reset system, which realizes effective arbitration and reset triggering when a double CPU system fails and improves the reliability and independence of system failure recovery. In order to solve the technical problems, the first technical scheme adopted by the invention is as follows: a dual CPU arbitration reset system comprises a first controlled power supply, a second controlled power supply, a first CPU, a second CPU, a first power supply control circuit and a second power supply control circuit; The input end of the first controlled power supply and the input end of the second controlled power supply are connected with an external main power supply; the output end of the first controlled power supply is connected with the power supply end of the first CPU, and the power supply enabling end of the first controlled power supply is connected with the general input and output end of the second CPU through the second power supply control circuit; The output end of the second controlled power supply is connected with the power supply end of the second CPU, and the power supply enabling end of the second controlled power supply is connected with the general input and output end of the first CPU through the first power supply control circuit; and a bidirectional heartbeat communication link used for mutually monitoring the running state is arranged between the first CPU and the second CPU. The second technical scheme adopted by the invention is as follows: A control method based on the dual CPU arbitration reset system comprises the following steps: s1, controlling the general input and output end of the first CPU to initialize to a high-resistance state, and controlling the general input and output end of the second CPU to initialize to the high-resistance state; s2, the first CPU and the second CPU monitor the running state through a bidirectional heartbeat communication link; If the first CPU judges that the second CPU fails, the first CPU executes a first reset arbitration operation on the second controlled power supply through a first power supply control circuit; And if the second CPU judges that the first CPU fails, the second CPU executes a second reset arbitration operation on the first controlled power supply through a second power supply control circuit. The invention has the beneficial effects that: The system ensures independent control of power supply of the two CPUs by arranging the first controlled power supply and the second controlled power supply which are mutually independent and respectively supply power to the first CPU and the second CPU, avoids mutual interference during reset operation, enables the first power supply control circuit and the second power supply control circuit to form a cross control framework, enables the second CPU to control the first controlled power supply through the first power supply control circuit, enables the first CPU to control the second controlled power supply through the second power supply control circuit, realizes accurate control of the power supply of the normal CPU to the fault CPU, and enables bidirectional heartbeat communication links between the first CPU and the second CPU to mutually monitor the running state in real time and reliably, provides direct basis for fault judgment, and enables effective arbitration and reset triggering during the fault of the double CPU system to be realized through cooperative cooperation of all modules in the whole framework, thereby improving reliability and i