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CN-122019277-A - Embedded chip simulation and debugging method and system

CN122019277ACN 122019277 ACN122019277 ACN 122019277ACN-122019277-A

Abstract

The invention relates to an embedded chip simulation and debugging method and system. The method comprises the following steps of expanding an instruction decoding module, a register description module and a breakpoint management module which support a C28x instruction set in a GDB debugger to generate a special debugging front-end program, expanding a C28x JTAG protocol adaptation module in OpenOCD debugging agents to generate a debugging agent program, realizing a C28x instruction set execution simulation unit in a NEMU simulator and embedding the simulation unit into a GDB Server communication module, and realizing seamless switching of a simulation debugging mode and a hardware debugging mode based on a unified configuration file through a software and hardware debugging environment rapid switching control module. The invention solves the problems that the traditional debugging mode depends on a special hardware simulator, has high cost and inaccurate simulation environment, greatly reduces the debugging cost and improves the development efficiency and the comprehensiveness of system verification by adopting an integrated software and hardware collaborative debugging scheme.

Inventors

  • LIU BAOZHOU
  • WU SHAOFENG
  • TIAN YE
  • CHEN LONGZHEN

Assignees

  • 中国电子科技集团公司第五十八研究所

Dates

Publication Date
20260512
Application Date
20251118

Claims (10)

  1. 1. The embedded chip simulating and debugging method is characterized by comprising the following steps: step S1, an instruction decoding module, a register description module and a breakpoint management module which support a C28x instruction set are expanded in a GDB debugger, and a GDB debugging front-end program aiming at a C28x architecture is generated; step S2, expanding a debugging adaptation module supporting a C28x chip in OpenOCD debugging agents, wherein the debugging adaptation module comprises a C28x JTAG protocol adaptation unit, and generating OpenOCD debugging agents supporting the C28x chip; Step S3, implementing an execution simulation unit of a C28x instruction set in a NEMU simulator framework, embedding a GDB Server communication module, and carrying out debugging instruction analysis and state feedback with the GDB debugging front-end program through a GDB remote serial protocol; and S4, a software and hardware debugging environment fast switching control module selects a simulation debugging mode or a hardware debugging mode based on a unified configuration file when the system is started, and seamless switching is realized under a unified debugging interface.
  2. 2. The method for simulating and debugging an embedded chip as claimed in claim 1, wherein the modules expanded in the GDB debugger specifically comprise: The method comprises the steps of S1-1, a target architecture description unit, a target-C28x.c, a register structure defining a C28x architecture, wherein the target architecture description unit adds a target description file target-C28x.c in a GDB source code, and the register structure comprises 32 general registers, 8 auxiliary registers, a status flag register ST0/ST1 and a stack pointer SP; The instruction decoding execution unit is used for realizing instruction decoding routine decode_c28x_ insn, analyzing instruction operation codes, immediate numbers and register operands based on a 16-bit instruction format of C28x, and supporting arithmetic operation, logical operation, branch jump and memory access instruction sets; And S1-3, adding a breakpoint management interface, rewriting a target_stop function, and returning a C28X_ SIGTRAP signal when the breakpoint is triggered by the breakpoint management control unit.
  3. 3. The embedded chip simulation and debugging method of claim 1, wherein the debugging adaptation module in OpenOCD debugging agents comprises: step S2-1, a JTAG configuration unit defines a JTAG TAP and a register access instruction in OpenOCD configuration files; S2-2, a protocol expansion unit expands JTAG protocol supporting C28x chip, defines JTAG scan chain and TAP state machine, and realizes CPU register access, program memory and data memory read-write function; Step S2-3, a Flash driving unit writes a Flash controller driving program, which comprises an erase_sector (), a write_word (), a check_status () function and directly operates a Flash controller register; And S2-4, a compiling and constructing unit modifies Makefile configuration, adds C28x architecture compiling options and generates a special debugging agent program.
  4. 4. The embedded chip simulation and debug method of claim 1, wherein the execution simulation unit in the NEMU simulator comprises: S3-1, a CPU state management subunit, wherein a CPU state structure body is newly added in a NEMU framework and comprises register states of all stages of a pipeline; S3-2, a pipeline scheduling subunit realizes a pipeline scheduling function pipeline_schedule () of C28x, simulates the pipeline execution process of an instruction, and integrates data conflict detection, control conflict processing and a pipeline forwarding mechanism; S3-3, a peripheral simulation subunit adopts an address mapping and callback registration mechanism to map the PWM module, the timer, the ADC and the SPI peripheral to a specific memory address space, and simulates peripheral behaviors through callback functions; s3-4, an interrupt simulation subunit checks an interrupt request queue in each pipeline period and timely responds to the interrupt request; And step S3-5, embedding the GDB Server communication subunit into the GDB Server to realize the functions of RSP protocol analysis, register read-write and memory read-write.
  5. 5. The embedded chip simulation and debugging method of claim 1, wherein the software and hardware debugging environment fast switching control module comprises: step S4-1, a configuration management unit sets GDB debugging targets and OpenOCD interface parameters in a unified configuration file of a PC end, and supports quick switching of simulation debugging and hardware debugging environments; the system comprises a NEMU (network management unit) built-in GDB (graphics device B) Server, a remote serial protocol (serial protocol) connection OpenOCD and a proxy module, wherein the GDB Server is connected with the NEMU built-in GDB Server through the remote serial protocol in a simulated debugging mode; and S4-2, a debugging monitoring unit realizes unified monitoring of simulation debugging and hardware debugging of the target program through the GDB debugging interface, and maintains consistency of the debugging interface, breakpoint configuration and variable mapping.
  6. 6. The embedded chip simulation and debug method as claimed in claim 4, wherein said GDB Server communication subunit comprises: The command analysis module analyzes a remote serial protocol command from the GDB debugging front end; the simulator control module controls the execution flow of the simulator according to the analyzed command, including pause, continuous, single step execution, register and memory access operation; And the state feedback module is used for feeding back the execution state of the simulator to the GDB debugging front end through the GDB remote serial protocol.
  7. 7. An embedded chip emulation and debug method according to claim 2, wherein said instruction decode routine decode_c28x_ insn comprises the steps of: based on the 16-bit instruction format of C28x, an instruction operation code field, a register number field and an immediate field are extracted; Performing sign expansion processing on the extracted immediate field to generate a 32-bit signed immediate; distinguishing arithmetic operation, logic operation, branch jump and memory access instructions according to the instruction type identified by the operation code field; And generating control signals required by instruction execution and submitting the control signals to the simulator execution unit.
  8. 8. The embedded chip simulation and debugging method of claim 4, wherein the pipeline scheduling function pipeline_schedule () implements the steps of: maintaining the states of all stages of pipeline registers, including an instruction fetching register, a decoding register, an execution register, a memory access register and a write-back register; executing a data conflict detection algorithm, and detecting RAW, WAR and WAW conflicts through register correlation analysis; Executing a control conflict processing mechanism, and performing target address prediction and pipeline flushing operation on the branch instruction; Adopting a pipeline forwarding mechanism to directly forward a front stage pipeline result to an instruction of a rear stage needing the result; and updating the states of the register stages at the end of each pipeline period, and advancing the simulation execution progress.
  9. 9. An embedded chip simulation and debug system, serving the method steps of any of claims 1 to 8, comprising: the PC is provided with a GDB debugging front-end program and OpenOCD debugging agent programs; a C28x target board comprising an embedded processor of a C28x architecture; JTAG debug interface, connect PC and C28x goal board; A C28x simulator based on NEMU realization, which runs in a PC; The GDB debugging front-end program is connected with a GDB Server module in the simulator through a GDB remote serial protocol, and issues a debugging command and receives simulation state feedback; The OpenOCD debugging agent program is a compiler program after expanding and supporting the C28x architecture, and is connected with and controls a C28x target board to carry out hardware debugging and state feedback through a JTAG interface; And the PC and the target board realize two-way communication through a JTAG interface, so that the software and hardware collaborative debugging and verification of the C28x chip are completed.
  10. 10. The embedded chip simulation and debugging system of claim 9, wherein the GDB debugging front end and OpenOCD debugging agents in the PC end share a unified configuration file, and the configuration file adopts a structured data format, including a debugging mode selection, interface parameters, a target architecture identification and a Flash security setting field, so that the embedded chip simulation and debugging system can be rapidly switched between a simulation debugging mode and a hardware debugging mode according to development requirements to provide an integrated debugging process.

Description

Embedded chip simulation and debugging method and system Technical Field The present invention relates to the field of electronic engineering technologies, and in particular, to a method and a system for simulating and debugging an embedded chip. Background With the wide application of embedded chips in the fields of industrial automation, power electronics and real-time control, the requirements for debugging and simulation verification of the embedded chips are higher and higher. The traditional debugging mode needs a special simulator, debugging software and a hardware platform, has high debugging cost, and is difficult to meet the requirements of quick development and low-cost application. In addition, most of the existing simulation environments are simple instruction level simulation, lack of fine simulation on pipeline, interrupt and peripheral behaviors, and cannot effectively support comprehensive system level verification. Therefore, the development of the high-efficiency and low-cost C28x chip simulation and debugging method and system for comprehensively supporting the rapid switching of the software and hardware environments has important practical significance. Disclosure of Invention The invention aims to provide an embedded chip simulation and debugging method and system, which are used for respectively increasing the support of a C28x architecture in three components of GDB, openOCD and NEMU, realizing a seamless switching mechanism of a software and hardware debugging environment, reducing the debugging cost and improving the development efficiency. In order to achieve the above purpose, the present invention provides an embedded chip simulation and debugging method, comprising the following steps: step S1, an instruction decoding module, a register description module and a breakpoint management module which support a C28x instruction set are expanded in a GDB debugger, and a GDB debugging front-end program aiming at a C28x architecture is generated; Step S2, expanding a debugging adaptation module supporting a C28x chip in OpenOCD debugging agents, wherein the debugging adaptation module comprises a C28xJTAG protocol adaptation unit, and generating OpenOCD debugging agents supporting the C28x chip; Step S3, implementing an execution simulation unit of a C28x instruction set in a NEMU simulator framework, embedding a GDB Server communication module, and carrying out debugging instruction analysis and state feedback with the GDB debugging front-end program through a GDB remote serial protocol; and S4, a software and hardware debugging environment fast switching control module selects a simulation debugging mode or a hardware debugging mode based on a unified configuration file when the system is started, and seamless switching is realized under a unified debugging interface. Preferably, the modules expanded in the GDB debugger specifically include: The method comprises the steps of S1-1, a target architecture description unit, a target-C28x.c, a register structure defining a C28x architecture, wherein the target architecture description unit adds a target description file target-C28x.c in a GDB source code, and the register structure comprises 32 general registers, 8 auxiliary registers, a status flag register ST0/ST1 and a stack pointer SP; The instruction decoding execution unit is used for realizing instruction decoding routine decode_c28x_ insn, analyzing instruction operation codes, immediate numbers and register operands based on a 16-bit instruction format of C28x, and supporting arithmetic operation, logical operation, branch jump and memory access instruction sets; And S1-3, adding a breakpoint management interface, rewriting a target_stop function, and returning a C28X_ SIGTRAP signal when the breakpoint is triggered by the breakpoint management control unit. Preferably, the debug adaptation module in the OpenOCD debug agent includes: step S2-1, a JTAG configuration unit defines a JTAG TAP and a register access instruction in OpenOCD configuration files; S2-2, a protocol expansion unit expands JTAG protocol supporting C28x chip, defines JTAG scan chain and TAP state machine, and realizes CPU register access, program memory and data memory read-write function; Step S2-3, a Flash driving unit writes a Flash controller driving program, which comprises an erase_sector (), a write_word (), a check_status () function and directly operates a Flash controller register; And S2-4, a compiling and constructing unit modifies Makefile configuration, adds C28x architecture compiling options and generates a special debugging agent program. Preferably, the execution simulation unit in the NEMU simulator includes: S3-1, a CPU state management subunit, wherein a CPU state structure body is newly added in a NEMU framework and comprises register states of all stages of a pipeline; S3-2, a pipeline scheduling subunit realizes a pipeline scheduling function pipeline_schedule () of C28x, simulates the p