CN-122019284-A - Virtual lower computer simulation test system and method

CN122019284ACN 122019284 ACN122019284 ACN 122019284ACN-122019284-A

Abstract

The application discloses a virtual lower computer simulation test system and a virtual lower computer simulation test method. The virtual lower computer simulation test system comprises a virtual serial port management module, an instruction processing module and a test response module, wherein the virtual serial port management module is used for dynamically creating and supporting parameter configuration and independent operation of various simulation test ports, receiving instructions of an upper computer through each simulation test port, analyzing the instructions in batches, distributing and processing the instructions according to the types or the contents of the instructions obtained through analysis, and the test response module is used for generating response back codes according to the contents of the instructions and feeding the response back codes back to the upper computer through the corresponding virtual serial port management module so as to complete the test of the upper computer. By the mode, the virtual serial port performance in the upper computer testing environment can be improved.

Inventors

Xie Zhizan
BU FANWEI
LI ZONGYAO

Assignees

深圳市有方科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20251231

Claims (10)

1. A virtual lower computer simulation test system, comprising: The virtual serial port management module is used for dynamically creating and supporting parameter configuration and independent operation of various simulation test ports and receiving instructions of the upper computer through each simulation test port; the instruction processing module is used for analyzing the instructions in batches, and distributing and processing the instructions according to the instruction types or the instruction contents obtained through analysis; And the test response module is used for generating a response return code according to the content of the instruction, and feeding back the response return code to the upper computer through the corresponding virtual serial port management module so as to complete the test of the upper computer.
2. The virtual lower computer simulation test system of claim 1, wherein the simulation test port types supported by the virtual serial port management module AT least comprise a download port, a universal asynchronous receiver-transmitter port, a microcontroller unit port, an AT command port, a global positioning system interface port, and a diagnostic port; the content of the parameter configuration comprises baud rate, data bit and check bit, and each simulation test port has unique port type identification.
3. The virtual lower computer simulation test system according to claim 1 or 2, wherein the virtual serial port management module supports dynamic creation of a plurality of simulation test ports of the same type, and distinguishes each simulation test port by an independent serial port ID to ensure that each port operates independently without interactive conflicts.
4. The virtual lower computer simulation test system according to claim 1, wherein the instruction processing module is provided with a built-in instruction analysis and distribution rule base supporting configuration, and the instruction processing module performs batch analysis on grammar verification and keyword extraction of batch instructions and distributes and processes the batch instructions based on the rule base matching instruction types or contents.
5. The virtual lower computer simulation test system according to claim 1 or 4, wherein the virtual serial port management module comprises a serial port route transmission unit, and the serial port route transmission unit is used for realizing data interaction between different simulation test ports; and the instruction processing module forwards the common instruction to the test response module, and routes the instruction needing transparent transmission to the serial port routing transparent transmission unit.
6. The virtual lower computer simulation test system according to claim 5, wherein the serial port routing transparent unit supports a custom bi-directional transparent rule and a uni-directional transparent rule, the bi-directional transparent rule is applicable to data interaction between an AT command port and a microcontroller unit port, and the uni-directional transparent rule is applicable to data forwarding from a global positioning system interface port to the AT command port.
7. The virtual lower computer simulation test system of claim 1, wherein the test response module supports generating a normal response return code and a customized abnormal response return code, the abnormal response return code comprising a timeout response, an error code response and a data loss simulation response, adapting to pressure test, boundary test and weak environment test scenarios.
8. The virtual lower computer simulation test system of claim 7, wherein the test response module further combines external analog input data or transparent data when generating the response code, wherein the external analog input data comprises at least one of meter data, sensor data, power supply voltage data and global positioning data.
9. The virtual lower computer simulation test system according to claim 1, further comprising a configuration and management interface, wherein the configuration and management interface is configured to configure the number and type of virtual serial ports, edit command parsing and distribution rules, set response modes, and support storage, import and export of all configuration parameters.
10. A virtual lower computer simulation test method for a virtual lower computer simulation test system according to any one of claims 1 to 9, comprising: establishing online connection with an upper computer through a simulation test port, so that the upper computer sends a debugging instruction to the virtual lower computer simulation test system through the simulation test port; receiving a debugging instruction and analyzing the debugging instruction in batches; distributing and processing the instruction according to the instruction type or the instruction content obtained by analysis, and generating a response return code according to the content of the instruction; and feeding the response code back to the upper computer through the virtual serial port management module so as to complete the test of the upper computer.

Description

Virtual lower computer simulation test system and method Technical Field The application relates to the field of serial communication, in particular to a virtual lower computer simulation test system and method. Background In the development process, the upper computer needs to be debugged online with the lower computer to verify the functions of the upper computer. However, in early stages of development, the lower computer is not ready for various reasons, and at this time, the upper computer cannot be developed and cannot be debugged online with the lower computer. The situation blocks the development progress of the upper computer software, influences the overall progress of projects, prolongs the time of product marketing, and possibly leads to the failure of the machine due to the time of product marketing after the bid. In the prior art, a virtual serial port is generally adopted to replace an entity lower computer to perform serial port test of an upper computer, the problem of single forwarding logic generally exists in the existing virtual serial port forwarding technology, and in a scene of sending batch instructions, the lack of distribution logic leads to difficulty in meeting test requirements of the virtual serial port. Meanwhile, when performing abnormal tests such as pressure test, boundary test and weak environment test, the virtual serial port in the prior art cannot effectively manage various abnormal test states. Disclosure of Invention The application mainly provides a virtual lower computer simulation test system and a virtual lower computer simulation test method, which aim to solve the problem of insufficient performance of a virtual serial port in an upper computer test environment. The technical scheme includes that the virtual serial port management module is used for dynamically creating and supporting parameter configuration and independent operation of various simulation test ports and receiving instructions of an upper computer through each simulation test port, the instruction processing module is used for analyzing the instructions in batches and distributing and processing the instructions according to instruction types or instruction contents obtained through analysis, and the test response module is used for generating response back codes according to the instruction contents and feeding the response back codes to the upper computer through the corresponding virtual serial port management module so as to finish testing of the upper computer. In some embodiments, the types of the analog test ports supported by the virtual serial port management module AT least comprise a download port, a universal asynchronous receiver-transmitter port, a microcontroller unit port, an AT command port, a global positioning system interface port and a diagnostic port, the content of the parameter configuration comprises baud rate, data bits and check bits, and each analog test port has a unique port type identifier. In some embodiments, the virtual serial port management module supports dynamically creating a plurality of analog test ports of the same type, and distinguishing each analog test port through an independent serial port ID, so as to ensure that each port operates independently without interaction conflict. In some embodiments, the instruction processing module is internally provided with an instruction analysis and distribution rule base supporting configuration, and the instruction processing module performs batch analysis on grammar verification and keyword extraction of batch instructions and distributes and processes the batch instructions based on the rule base matching instruction types or contents. In some embodiments, the virtual serial port management module comprises a serial port routing transparent unit, wherein the serial port routing transparent unit is used for realizing data interaction among different simulation test ports, and the instruction processing module forwards a common instruction to the test response module and routes the instruction needing transparent transmission to the serial port routing transparent unit. In some embodiments, the serial port routing transparent unit supports a custom bi-directional transparent rule and a uni-directional transparent rule, the bi-directional transparent rule is applicable to data interaction between an AT command port and a microcontroller unit port, and the uni-directional transparent rule is applicable to data forwarding from a global positioning system interface port to the AT command port. In some embodiments, the test response module supports generating normal response back codes and customized abnormal response back codes, the abnormal response back codes comprising timeout responses, error code responses and data loss simulation responses, adapting to pressure test, boundary test and weak environment test scenarios. In some embodiments, the test response module further incorporates external analog input data