CN-122019285-A - Chip testing method and device

CN122019285ACN 122019285 ACN122019285 ACN 122019285ACN-122019285-A

Abstract

The application relates to a chip testing method and device. The method comprises the steps of responding to a test configuration instruction, determining a node to be tested in the master node and the slave node and a test channel in the channels, wherein the test channel is a channel for configuring a test event according to the test configuration instruction and is a channel connected with the node to be tested, the test event comprises a back pressure event or an error injection event, an original signal corresponding to the test channel of the node to be tested is replaced through a test signal corresponding to the test event, the test signal is sent to the node corresponding to the test event through the test channel, and after the feedback signal aiming at the test signal is obtained and processed by the node to be tested, a test result of the node to be tested is determined according to conditions met by the node to be tested. The method can improve the accuracy and efficiency of chip testing.

Inventors

TENG FENG
ZHAO YE
ZHANG FUYUN

Assignees

无锡众星微系统技术有限公司

Dates

Publication Date: 20260512
Application Date: 20260107

Claims (10)

1. A chip testing method, applied to a target chip, the target chip including a master node and a slave node, there being a plurality of channels between the master node and the slave node, the method comprising: Responding to a test configuration instruction, determining nodes to be tested in the master node and the slave nodes and test channels in the channels, wherein the test channels are channels for configuring a test event according to the test configuration instruction and are channels connected with the nodes to be tested; Replacing an original signal corresponding to the test channel of the node to be tested by a test signal corresponding to the test event, and sending the test signal to the node corresponding to the test event by the test channel; after the node to be tested obtains and processes the feedback signal aiming at the test signal, determining a test result of the node to be tested according to the condition met by the node to be tested.
2. The method according to claim 1, wherein replacing the original signal corresponding to the node to be tested in the test channel by the test signal corresponding to the test event comprises: Under the condition that a test signal corresponding to the test event represents a test command request, acquiring an original command request corresponding to the test channel of the node to be tested, wherein the original command request is a command request for indicating a slave node to process and feed back a response result, and the test command request is a command request for indicating the slave node to process according to the back pressure event or the fault injection event and feed back the response result; and replacing the original command request with the test command request.
3. The method according to claim 1, wherein replacing the original signal corresponding to the node to be tested in the test channel by the test signal corresponding to the test event comprises: Under the condition that a test signal corresponding to the test event represents a test response result, acquiring an original response result corresponding to the node to be tested in the test channel, wherein the original response result is a response result obtained by the slave node based on original command request processing; And replacing the original response result with the test response result.
4. The method according to claim 1, wherein the method further comprises: determining a time parameter corresponding to the back pressure event under the condition that the test event is the back pressure event; And generating a back pressure test signal corresponding to the back pressure event according to the time corresponding to the time parameter, wherein the back pressure test signal belongs to the test signal.
5. The method according to claim 1, wherein the method further comprises: When the node to be tested is a slave node and the node to be tested does not have a corresponding master node, responding to a proxy test configuration instruction, and determining a proxy test channel between a processor and the node to be tested; Transmitting a test signal corresponding to the proxy test event to the node to be tested through the proxy test channel; after the node to be tested obtains and processes the feedback signal aiming at the test signal, determining the proxy test result of the node to be tested according to the condition satisfied by the node to be tested.
6. The method of claim 1, wherein in the event that the test event is the backpressure event, the test signal comprises a backpressure test signal representing no instruction, the backpressure test signal being a signal sent to the slave node.
7. The method of claim 1, wherein the test signal comprises a fault injection test request or a fault injection test response result corresponding to the fault injection event in the case that the test event is the fault injection event, the fault injection test request is sent to a slave node corresponding to the test event, and the fault injection test response result is sent to a master node corresponding to the test event.
8. A chip testing apparatus for use with a target chip, the target chip comprising a master node and a slave node, a plurality of lanes being present between the master node and the slave node, the apparatus comprising: The configuration module is used for responding to a test configuration instruction, determining the nodes to be tested in the master node and the slave nodes and the test channels in the channels, wherein the test channels are channels for configuring a test event according to the test configuration instruction and are channels connected with the nodes to be tested; The control module is used for replacing an original signal corresponding to the test channel of the node to be tested through the test signal corresponding to the test event, and sending the test signal to the node corresponding to the test event through the test channel; the test module is used for determining the test result of the node to be tested according to the condition met by the node to be tested after the node to be tested obtains and processes the feedback signal aiming at the test signal.
9. The apparatus of claim 8, wherein the control module is configured to: Under the condition that a test signal corresponding to the test event represents a test command request, acquiring an original command request corresponding to the test channel of the node to be tested, wherein the original command request is a command request for indicating a slave node to process and feed back a response result, and the test command request is a command request for indicating the slave node to process according to the back pressure event or the fault injection event and feed back the response result; and replacing the original command request with the test command request.
10. The apparatus of claim 8, wherein the control module is further configured to: Under the condition that a test signal corresponding to the test event represents a test response result, acquiring an original response result corresponding to the node to be tested in the test channel, wherein the original response result is a response result obtained by the slave node based on original command request processing; And replacing the original response result with the test response result.

Description

Chip testing method and device Technical Field The present application relates to the field of circuit testing, and in particular, to a method and apparatus for testing a chip. Background With the continuous development of chip technology, on-chip interconnection technology represented by AMBA (advanced microcontroller bus architecture) appears, and chips generally rely on AMBA bus or similar interconnection technology to realize internal module communication. Often, these technologies do not use a single bus, but rather include sub-protocols adapted to different scenarios, for example, a SoC chip may integrate AXI, AHB, APB, etc. protocols as required, which are used for communication between a high performance module, a medium performance module, and a low-speed high-stability peripheral. In the chip design process, an adaptation protocol can be selected according to factors such as performance requirements, power consumption constraint, interface complexity and the like to form a layered interconnection architecture, for example, an AXI (advanced extensible interface) is used as a high-performance layer, an APB (advanced peripheral interface) is used as a low-power peripheral layer, and cross-layer communication is realized through a bridge. Therefore, the hierarchical interconnection architecture of the chip may cause different types of abnormal situations such as time sequence conflict, abnormal bus arbitration, cross-layer data transmission errors and the like in the stages of design verification, back-slice test and the like. In the traditional technology, the abnormality is often detected through the aging test or the function traversal test of the chip running for a long time, and the deep defect is difficult to locate in the mode, so that the precision and the efficiency of the chip test are required to be improved. Disclosure of Invention Accordingly, it is desirable to provide a method and apparatus for testing chips, which can improve the accuracy and efficiency. In a first aspect, the present application provides a chip testing method applied to a target chip, where the target chip includes a master node and a slave node, and multiple channels exist between the master node and the slave node, and the method includes: Responding to a test configuration instruction, determining nodes to be tested in the master node and the slave nodes and test channels in the channels, wherein the test channels are channels for configuring a test event according to the test configuration instruction and are channels connected with the nodes to be tested; Replacing an original signal corresponding to the test channel of the node to be tested by a test signal corresponding to the test event, and sending the test signal to the node corresponding to the test event by the test channel; after the node to be tested obtains and processes the feedback signal aiming at the test signal, determining a test result of the node to be tested according to the condition met by the node to be tested. In a second aspect, the present application also provides a chip testing apparatus applied to a target chip, where the target chip includes a master node and a slave node, and a plurality of channels exist between the master node and the slave node, and the apparatus includes: The configuration module is used for responding to a test configuration instruction, determining the nodes to be tested in the master node and the slave nodes and the test channels in the channels, wherein the test channels are channels for configuring a test event according to the test configuration instruction and are channels connected with the nodes to be tested; The control module is used for replacing an original signal corresponding to the test channel of the node to be tested through the test signal corresponding to the test event, and sending the test signal to the node corresponding to the test event through the test channel; the test module is used for determining the test result of the node to be tested according to the condition met by the node to be tested after the node to be tested obtains and processes the feedback signal aiming at the test signal. The method and the device for testing the chip, which respond to the test configuration instruction, determine the nodes to be tested in the master node and the slave node and the test channels in the channels, so that the target chip has the function of supporting the configuration of the nodes to be tested and the test channels, and ensure that each node of the target chip is decoupled in the test process of the target chip through the function, so that each node can be tested respectively, thereby ensuring the accuracy. Furthermore, the original signals corresponding to the nodes to be tested in the test channels are replaced by the test signals corresponding to the test events, and the sudden back pressure situation or the fault injection situation of the master node and the slave node in the sign