CN-122019287-A - Low-power consumption SRAM data retention self-checking method, controller and system on chip

CN122019287ACN 122019287 ACN122019287 ACN 122019287ACN-122019287-A

Abstract

The invention provides a low-power-consumption SRAM data retention self-checking method, a controller and a system on a chip, and relates to the technical field of low-power-consumption design, wherein the SRAM comprises a first voltage domain and a second voltage domain, all storage data of the SRAM are read under the second voltage domain before the SRAM enters a low-power-consumption state, and a first characteristic value corresponding to the read first storage data is stored in the first voltage domain; after the SRAM wakes up from the low power consumption state and the second voltage domain is electrified again, all the stored data of the SRAM are read again under the second voltage domain, the second characteristic value corresponding to the read second stored data is compared with the first characteristic value stored in the first voltage domain in consistency, and a self-checking result of whether the data of the SRAM are lost in the low power consumption state is determined according to the consistency result. Thus, quick and reliable self-checking on whether SRAM data is lost in a low-power consumption holding state is realized.

Inventors

JIANG ZHENGZHONG

Assignees

上海物骐微电子有限公司
重庆物奇科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260130

Claims (10)

1. The low-power-consumption SRAM data retention self-checking method is characterized in that the SRAM comprises a first voltage domain and a second voltage domain, and comprises the following steps: before the SRAM enters a low power consumption state, reading all storage data of the SRAM in the second voltage domain, and storing a first characteristic value corresponding to the read first storage data into the first voltage domain, wherein after the SRAM enters the low power consumption state, the second voltage domain is powered down; After the SRAM wakes up from the low power consumption state and the second voltage domain is electrified again, all the stored data of the SRAM are read again under the second voltage domain, the second characteristic value corresponding to the read second stored data is compared with the first characteristic value stored in the first voltage domain in consistency, and a self-checking result of whether the data of the SRAM are lost in the low power consumption state is determined according to the consistency result.
2. The method of claim 1, wherein storing the first characteristic value corresponding to the read first storage data in the first voltage domain comprises: calculating the first stored data by adopting an accumulation algorithm or an encryption hash algorithm to obtain the first characteristic value; the first characteristic value is stored to the first voltage domain.
3. The low power SRAM data retention self test method of claim 2, wherein said storing said first characteristic value into said first voltage domain comprises: The first characteristic value is latched to the first voltage domain by a latch.
4. The method of claim 1, wherein the step of comparing the second characteristic value corresponding to the read second stored data with the first characteristic value stored in the first voltage domain, and determining the self-checking result of whether the SRAM loses data in the low power state according to the consistency comparison result comprises: calculating the second stored data by adopting an accumulation algorithm or an encryption hash algorithm to obtain the second characteristic value; Reading the first characteristic value from the latch of the first voltage domain; Comparing the first characteristic value with the second characteristic value to obtain a consistency result; When the consistency result is consistent with the self-checking result, determining that the self-checking result is that the data is not lost; And when the consistency result is that the two are not consistent, determining that the self-checking result is that data loss exists.
5. A low power SRAM data retention self-test device, the SRAM comprising a first voltage domain and a second voltage domain, the low power SRAM data retention self-test device comprising: The storage module is used for reading all storage data of the SRAM under the second voltage domain before the SRAM enters a low power consumption state and storing a first characteristic value corresponding to the read first storage data into the first voltage domain, wherein after the SRAM enters the low power consumption state, the second voltage domain is powered down; And the self-checking module is used for re-reading all the storage data of the SRAM under the second voltage domain after the SRAM wakes up from the low power consumption state and the second voltage domain is electrified again, comparing the consistency of the second characteristic value corresponding to the read second storage data with the first characteristic value stored in the first voltage domain, and determining a self-checking result of whether the data of the SRAM is lost or not under the low power consumption state according to the consistency result.
6. The low power consumption SRAM data retention self-test device of claim 5, wherein the memory module is configured to calculate the first stored data using an accumulation algorithm or a cryptographic hash algorithm to obtain the first characteristic value, and store the first characteristic value into the first voltage domain.
7. The low power SRAM data retention self test device of claim 6, wherein the memory module is further configured to latch the first characteristic value to the first voltage domain via a latch.
8. The low-power consumption SRAM data retention self-checking device according to claim 5, wherein the self-checking module is specifically configured to calculate the second stored data by using an accumulation algorithm or a cryptographic hash algorithm to obtain the second characteristic value, read the first characteristic value from the latch of the first voltage domain, compare the first characteristic value with the second characteristic value to obtain a consistency result, determine that the self-checking result is that the data is not lost when the consistency result is that the two are consistent, and determine that the self-checking result is that the data is lost when the consistency result is that the two are not consistent.
9. A controller comprising a memory, a processor, the memory having stored therein a computer program executable on the processor, wherein the processor implements the low power SRAM data retention self test method of any one of claims 1-4 when the computer program is executed by the processor.
10. A system on a chip comprising the controller of claim 9, further comprising an SRAM coupled to the controller.

Description

Low-power consumption SRAM data retention self-checking method, controller and system on chip Technical Field The invention relates to the technical field of low-power design, in particular to a low-power SRAM data retention self-checking method, a controller and a system on a chip. Background In ultra low power SRAM (Static Random Access Memory) designs, two power rings (power rings) are typically provided, one for the power supply of the memory bank (labeled VCC) and the other for the external read-write logic (labeled VCCP). In ultra low power chip designs, a low power sleep (sleep) mode is supported that allows SRAM storage to enter a low power retention state. In this state, although VCC of SRAM is kept on, it is reduced to maintain data unchanged, and VCCP is turned off to save power consumption. The mode can realize extremely low static power consumption under the condition of keeping data not lost, thereby remarkably prolonging the standby time, and the system can be quickly awakened from a sleep state and restored to operate because the information such as software programs, data and the like are kept (namely, the data is not lost). However, as process technology advances, data retention stability in such low power states is challenging. On the one hand, chip designers tend to reduce the data retention voltage as much as possible in order to obtain better power consumption benefits, and on the other hand, the power supply robustness between the chip internal power supply loop and the external wiring is inconsistent, and together with factors such as ripple and disturbance, the risk of data loss is increased. Therefore, in a complex SoC (System on Chip), a mechanism is needed to detect the data loss that may occur in such a low power state. Disclosure of Invention The invention aims to provide a low-power-consumption SRAM data retention self-checking method, a controller and a system-on-chip, so as to realize quick and reliable self-checking on whether SRAM data is lost or not in a low-power-consumption retention state. In a first aspect, the present invention provides a low power consumption SRAM data retention self-checking method, the SRAM includes a first voltage domain and a second voltage domain, the low power consumption SRAM data retention self-checking method includes: Before the SRAM enters a low power consumption state, reading all storage data of the SRAM in a second voltage domain, and storing a first characteristic value corresponding to the read first storage data into the first voltage domain, wherein after the SRAM enters the low power consumption state, the second voltage domain is powered down; After the SRAM wakes up from the low power consumption state and the second voltage domain is electrified again, all the stored data of the SRAM are read again under the second voltage domain, the second characteristic value corresponding to the read second stored data is compared with the first characteristic value stored in the first voltage domain in consistency, and a self-checking result of whether the data of the SRAM are lost in the low power consumption state is determined according to the consistency result. In an alternative embodiment, storing the first characteristic value corresponding to the read first storage data in the first voltage domain includes: calculating the first stored data by adopting an accumulation algorithm or an encryption hash algorithm to obtain a first characteristic value; The first characteristic value is stored to a first voltage domain. In an alternative embodiment, storing the first characteristic value to the first voltage domain comprises: the first characteristic value is latched to a first voltage domain by a latch. In an alternative embodiment, consistency comparison is performed on a second characteristic value corresponding to the read second stored data and a first characteristic value stored in the first voltage domain, and according to a consistency comparison result, a self-checking result of whether the SRAM loses data in a low power consumption state is determined, including: calculating the second stored data by adopting an accumulation algorithm or an encryption hash algorithm to obtain a second characteristic value; Reading a first characteristic value from a latch of a first voltage domain; comparing the first characteristic value with the second characteristic value to obtain a consistency result; when the consistency result is consistent with the data, determining that the self-checking result is that the data is not lost; And when the consistency result is that the two are not consistent, determining that the self-checking result is that the data loss exists. In a second aspect, the present invention provides a low power consumption SRAM data retention self-test device, the SRAM including a first voltage domain and a second voltage domain, the low power consumption SRAM data retention self-test device comprising: the storage module