CN-122019288-A - Chip testing method based on multi-protocol burning and self-adaptive testing

CN122019288ACN 122019288 ACN122019288 ACN 122019288ACN-122019288-A

Abstract

The invention relates to the technical field of chip testing, in particular to a chip testing method based on multi-protocol burning and self-adaptive testing, which comprises the steps of obtaining communication establishment time and communication stability rate based on testing modes corresponding to different types of physical interfaces, determining the characteristic state of a chip based on the communication establishment time and the communication stability rate, extracting equivalent impedance factor values of all chips in a first characteristic state to obtain an impedance threshold value enabling the chips to fall into the first characteristic state, determining the process drift index of chips in the current batch based on the comparison result of the equivalent impedance factor values and the impedance threshold value, determining whether the process fluctuation of the chips has process drift based on the process drift index, and adjusting and determining the critical upper limit value of the characteristic state of the chips. The invention realizes accurate excitation of hidden defects and self-adaptive calibration of process drift through multiprotocol transverse comparison diagnosis, on-chip impedance reverse-pushing and design tolerance-production line threshold dynamic closed loop.

Inventors

XU JIANWEI
BI HENGCHANG
Ning Shuya
YIN HONGBIN
ZHANG JUN
WANG JIANTAO
WANG CHUANZHONG
WANG YAOHUI
LEI GUOPING
LUO ZHONGWU
Ye Defan

Assignees

重庆宇隆光电科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260407

Claims (10)

1. A chip testing method based on multi-protocol burning and self-adaptive testing is characterized by comprising the following steps: Acquiring communication establishment time and communication stability rate based on test modes corresponding to different types of physical interfaces so as to determine the characteristic state of the chip, wherein the characteristic state of the chip comprises three types of physical characteristic states including wake-up delay of a USB interface, insufficient SPI transmission rate or global process deviation; Applying a first stress scheme based on the characteristic state, wherein the first stress scheme is used for adjusting the junction temperature of a chip to be higher than Wen Tezheng ℃, acquiring a wake-up time temperature sensitivity coefficient and a load jump transient recovery time to determine the severity of wake-up delay of a USB interface, and adjusting the power supply voltage to determine the voltage lifting amount required by the determination; Applying a second stress scheme based on the characteristic state, wherein the second stress scheme obtains variation coefficients of a plurality of actual transmission rates for adjusting an electrical load of the SPI interface, determines the severity of insufficient transmission rates of the SPI interface by combining the total number of read-back data errors, and adjusts the SPI communication clock frequency; The method comprises the steps of controlling the load state of core load current of a chip based on a first stress scheme, obtaining core current and USB wake-up time corresponding to different load states, determining a first impedance factor and a second impedance factor to obtain an equivalent impedance factor, wherein the first impedance factor is calculated according to the idle core current and the USB wake-up time corresponding to single core current, and the second impedance factor is calculated according to the USB wake-up time corresponding to single core current and double core current; Acquiring a nonlinear index based on the first impedance factor and the second impedance factor to determine the impedance characteristic of the chip, and adjusting the design value of the sensitivity coefficient of the power supply voltage, wherein the nonlinear index is the absolute value of the difference value of the first impedance factor and the second impedance factor; Extracting equivalent impedance factor values of all chips in a first characteristic state to obtain an impedance threshold value enabling the chips to fall into the first characteristic state, and determining a process drift index of the current batch of chips based on a comparison result of the equivalent impedance factor values and the impedance threshold value, wherein the chip characteristic of the first characteristic state is a wake-up delay of a USB interface; and determining whether the chip process fluctuation is process drift or not based on the process drift index, and adjusting and determining the critical upper limit value of the characteristic state of the chip.
2. The method for testing a chip based on multi-protocol burn-in and adaptive testing according to claim 1, wherein the determining the characteristic state of the chip comprises: If the communication establishment time of the USB interface exceeds the critical upper limit value of the history range and the communication establishment time of the JTAG interface and the SPI interface and the communication stable rates of the USB interface and the JTAG interface and the SPI interface are all in the respective history ranges, the chip is in a first characteristic state, and the chip characteristics are wake-up delay of the USB interface; If the communication stable rate of the SPI interface is lower than the critical lower limit value of the history range, and the communication establishment time of the JTAG interface, the SPI interface and the USB interface, and the communication stable rate of the USB interface and the JTAG interface are all in the respective history range, the chip is judged to be in a second characteristic state, and the chip characteristics are that the SPI interface transmission rate is insufficient.
3. The chip test method based on the multi-protocol burning and the self-adaptive test according to claim 2, wherein if the communication setup time of the three groups of interfaces is significantly larger and the communication stability rates of the three groups of interfaces are significantly smaller, the chip is judged to be in a third characteristic state, and the chip characteristics are that the overall clock is slow or the overall process is biased; When the communication stable rates of the three groups of interfaces are lower than the critical lower limit value of the corresponding history range, the communication stable rates of the three groups of interfaces are obviously smaller.
4. The method for testing a chip based on multi-protocol burn-in and adaptive testing of claim 3, wherein determining the severity of the wake-up delay of the USB interface comprises: If the temperature sensitivity coefficient of the wake-up time is larger than the first sensitivity coefficient threshold value and the transient recovery time of the load jump is larger than the first load recovery threshold value, judging that the severity of the wake-up delay of the USB interface is severe, and voltage compensation is needed; If the temperature sensitivity coefficient of the wake-up time is larger than the second sensitivity coefficient threshold value or the transient recovery time of the load jump is larger than the second load recovery threshold value, judging the severity of the wake-up delay of the USB interface to be moderate, and sending out a voltage compensation reference signal.
5. The method for testing a chip based on multi-protocol burn-in and adaptive testing of claim 4, wherein determining the severity of the insufficient transmission rate of the SPI interface comprises: Recording the total times of the read-back data errors in the plurality of tests, and if the proportion value of the total times in the plurality of tests is larger than the proportion threshold value, judging that the severity of the insufficient transmission rate of the SPI interface is serious, and marking the chip as waste; If the ratio value of the total times in the tests is smaller than the ratio threshold value and the variation coefficient is larger than or equal to the coefficient threshold value, judging the severity of the insufficient transmission rate of the SPI interface as moderate, starting down-conversion compensation, and reducing the SPI communication clock frequency.
6. The chip testing method based on multi-protocol burning and self-adaptive testing according to claim 5, wherein the core currents corresponding to different load states comprise idle core current and single-core current dual-core current; calculating a first impedance factor according to the USB wake-up time corresponding to the idle core current and the single core current, and calculating a second impedance factor according to the USB wake-up time corresponding to the single core current and the dual core current; And obtaining an equivalent impedance factor, wherein the equivalent impedance factor is an average value of the first impedance factor and the second impedance factor.
7. The method for testing a chip based on multi-protocol burn-in and adaptive testing of claim 6, wherein calculating an impedance deviation is recorded as a nonlinear index, the impedance deviation being an absolute value of a difference between a first impedance factor and a second impedance factor; If the nonlinear index is larger than the difference evaluation value, judging that the nonlinear impedance characteristic exists in the chip, waking up the chip for delay due to PDN process deviation under the sensitivity coefficient of the current power supply voltage of the chip, and outputting a design value for suggesting to reduce the sensitivity coefficient of the power supply voltage.
8. The method for testing a chip based on multi-protocol burn-in and adaptive testing of claim 7, wherein an impedance threshold is obtained for an equivalent impedance factor that causes the chip to fall into a first characteristic state; If the ratio of the first characteristic state marked by the chip is larger than the ratio threshold when the equivalent impedance factor value is larger than any equivalent threshold, judging that the tolerance upper limit of the USB interface to the PDN impedance is the corresponding equivalent threshold.
9. The method of claim 8, wherein the process drift index of the current lot of chips is calculated when any equivalent impedance factor is greater than a tolerance upper limit.
10. The method for testing a chip based on multi-protocol burn-in and adaptive testing of claim 9, wherein determining whether the chip process fluctuation is a process drift comprises: If the process drift index is smaller than or equal to the first index threshold, judging that the process fluctuation is in a normal range, and maintaining the existing threshold unchanged; if the process drift index is larger than the first index threshold and smaller than or equal to the second index threshold, judging the chip process drift, and adjusting the critical upper limit value; If the process drift index is larger than the second index threshold, judging that the chip process is seriously abnormal, and giving out a process abnormality alarm.

Description

Chip testing method based on multi-protocol burning and self-adaptive testing Technical Field The invention relates to the technical field of chip testing, in particular to a chip testing method based on multi-protocol burning and self-adaptive testing. Background With the rapid development of the fields of industrial Internet of things, intelligent automobiles, high-performance computing and the like, the application scene of the chip is extended from a single and controllable environment to a real physical world with complex and changeable conditions and severe working conditions. One microcontroller may need to initiate vehicle-mounted communications instantaneously in-40 ℃ severe cold, or may need to process multiple sensor data and high-speed network transmissions simultaneously at 85 ℃ high temperature. This presents an unprecedented challenge to the dynamic stability and energy efficiency matching of the chip under full life cycle, full operating conditions. The chip test is used as the last barrier for guaranteeing the product quality, and the core task of the chip test is changed from screening out chips capable of working into screening out chips capable of reliably working in complex scenes. However, as the chip application scenario becomes increasingly complex, the existing test methods face two fundamental contradictions that are difficult to reconcile: 1. The contradiction between static test and dynamic failure, the traditional test is usually carried out under the condition of fixed load and normal temperature, and the passing/failing is taken as a binary criterion. However, a large number of field failure cases indicate that the hidden fault of the chip is often only excited under the combined condition of specific load mutation and high-temperature stress. Such dynamic failures cannot be captured by static testing, resulting in a quality dilemma of "line pass, field failure". 2. The contradiction between unified standard and individual deviation is influenced by the tiny fluctuation of the manufacturing process, and the electrical characteristics (such as dynamic voltage drop response and critical stable voltage) of each chip have objective difference. However, the current test applies exactly the same nominal test parameters to all chips. This results in the potential risk being unrecognized for a chip with a weaker characteristic and the energy efficiency potential being wasted for a chip with a better characteristic. This "one-shot" mode is essentially a compromise in test accuracy to process variation. The root cause of the contradiction is that the existing test system does not have the capability of active excitation-quantitative diagnosis-individual compensation, so that the stability margin of the chip cannot be dynamically evaluated under specific stress, and the unique optimal working parameters cannot be given to each chip based on the actual measurement difference. Therefore, a new chip testing method capable of actively constructing a dynamic stress scene, quantitatively extracting individual characteristic boundaries, and realizing parameter-level personalized adaptation is needed. The Chinese patent publication No. CN101008909A discloses a chip and a chip testing method, wherein the chip is applied to a computer system, two ends of the chip are respectively connected with a high-speed bus and a low-speed bus, the chip comprises a testing control unit, an upstream component control unit, a downstream component control unit and a downstream component control unit, wherein the testing control unit is provided with preset address data and receives an external signal transmitted by the low-speed bus, and determines whether the address data of the external signal is compared with the preset address data according to a control signal, the upstream component control unit is connected with the high-speed bus and the testing control unit and is used for transmitting the external signal to the high-speed bus, and the downstream component control unit is connected with the high-speed bus and the testing control unit and is used for transmitting the external signal to the low-speed bus. From this, the chip and the chip testing method have the following problems: Conventional pass/fail tests have difficulty capturing hidden faults that are triggered under specific load and temperature combinations, and each chip has different optimal operating points (such as lowest stable voltage) due to small manufacturing differences, so that performance waste or potential risks are caused by unified nominal parameter tests. Disclosure of Invention Therefore, the invention provides a chip testing method based on multi-protocol burning and self-adaptive testing, which is used for solving the problems that in the prior art, the testing is difficult to capture hidden faults which are triggered under specific load and temperature combination, and the unified nominal parameter testing can cause performance