CN-122019289-A - FPGA device, testing system and method

CN122019289ACN 122019289 ACN122019289 ACN 122019289ACN-122019289-A

Abstract

The invention provides an FPGA device, a testing system and a method, wherein the FPGA device comprises at least two signal acquisition modules, a processing module, an interconnection module and a controller, wherein the at least two signal acquisition modules are used for synchronously sampling received input signals based on synchronous sampling clocks to obtain corresponding sampling data, the processing module is used for distributing storage addresses to the sampling data obtained by sampling each signal acquisition module according to different storage address intervals of external storage particles, the interconnection module is used for receiving the sampling data with different clock frequencies and corresponding storage addresses transmitted by each signal acquisition module, transmitting the sampling data and the corresponding storage addresses according to the working clock frequency of the controller, and the controller is used for receiving the sampling data and the corresponding storage addresses transmitted by the interconnection module and writing the sampling data into the external storage particles according to the storage addresses corresponding to the sampling data. The FPGA device can improve the bandwidth utilization rate of the written data and the storage capacity utilization rate.

Inventors

SUN YONGQIN
CHEN ZHIKAI
ZHOU LEI

Assignees

合肥康芯威存储技术有限公司

Dates

Publication Date: 20260512
Application Date: 20260414

Claims (10)

1. An FPGA device, comprising: The signal acquisition modules are used for receiving input signals with different clock frequencies, are configured with synchronous sampling clocks with the same clock frequency as the corresponding input signals, and synchronously sample the received input signals based on the synchronous sampling clocks to obtain corresponding sampling data; The processing module is used for distributing storage addresses to the sampled data obtained by sampling each signal acquisition module according to different storage address intervals of the external storage particles; the interconnection module is used for receiving the sampling data with different clock frequencies and the corresponding storage addresses transmitted by each signal acquisition module, and transmitting the sampling data and the corresponding storage addresses at the working clock frequency of the controller; and the controller is used for receiving the sampling data and the corresponding storage address transmitted by the interconnection module and writing the sampling data into the external storage particles according to the storage address corresponding to the sampling data.
2. The FPGA device of claim 1, wherein the signal acquisition module is further configured to access a working clock corresponding to an input signal in the module to be observed, and use the working clock as a synchronous sampling clock of the working clock to synchronously sample the input signal.
3. The FPGA device of claim 1, wherein the processing module is further configured to sequentially allocate, in a storage address interval corresponding to the signal acquisition module, corresponding storage addresses to the sampled data according to a generation sequence of the sampled data obtained by sampling by the signal acquisition module; the storage address intervals corresponding to the signal acquisition modules are a section of fixed and continuous address range in the external storage particles, and the storage address intervals corresponding to different signal acquisition modules are not overlapped with each other.
4. The FPGA device of claim 3 wherein the processing module is further configured to compare the memory address with a last memory address of the corresponding memory address interval after allocating the corresponding memory address to the sampled data, and to continue allocating the memory address to the next sampled data for a first memory address of the memory address interval when the memory address is the same as the last memory address of the corresponding memory address interval, thereby forming a continuous circular allocation of memory addresses of the sampled data.
5. The FPGA device of claim 1, wherein the interconnection module is further configured to sequentially transmit the sampled data corresponding to the plurality of signal acquisition modules and the storage addresses thereof according to a priority order preset by the plurality of signal acquisition modules when the plurality of signal acquisition modules simultaneously transmit the sampled data.
6. A test system for an FPGA device, comprising: the FPGA device of any of claims 1 to 5, configured to receive signals to be observed transmitted by a module to be tested at different clock frequencies, sample the signals to be observed to obtain sampled data, and write the sampled data into an external storage granule; The host is used for reading out the sampling data stored in the external storage particles through a readback interface of the interconnection module in the FPGA device and generating an actual waveform file from the read sampling data; the host is also used for comparing the actual waveform file with the simulation waveform file of the signal to be observed, and generating test information of the FPGA device based on a comparison result.
7. The system for testing an FPGA device of claim 6, wherein the host is further configured to obtain a storage address range corresponding to the signal acquisition module in the FPGA device on the external storage granule, and obtain a storage address allocated to sampling data of the signal acquisition module; When the storage addresses of all the sampling data are in continuous incremental distribution in the storage address interval, sequentially reading the sampling data from the storage address interval according to the storage addresses allocated by the sampling data; otherwise, confirming the start address and the end address of the sampling data in the storage address interval, and sequentially reading the sampling data from the storage address interval according to the start address and the end address of the sampling data.
8. The system of claim 7, wherein the host is further configured to read out sampling data from each storage address interval of the external storage granule, and generate an independent actual waveform file, respectively, where the actual waveform file corresponding to the sampling data in each storage address interval is used to compare with the simulated waveform file corresponding to the signal to be observed by the sampling data.
9. The FPGA device testing system of claim 7, wherein the host is further configured to use a common multiple of clock frequencies of sampled data in the plurality of signal acquisition modules as a global observation frequency, and calculate a ratio between the global observation frequency and the clock frequencies of the sampled data in each signal acquisition module to obtain an interpolation multiple of the sampled data in each signal acquisition module; The host is also used for copying and interpolating the sampling data in each storage address interval according to the corresponding interpolation multiple, generating a unified actual waveform file according to all the copied and interpolated sampling data, and comparing the unified actual waveform file with the simulation waveform files of all the signals to be observed.
10. A method for testing an FPGA device, using the FPGA device of any one of claims 1 to 5, comprising: receiving signals to be observed transmitted by a module to be tested at different clock frequencies through the FPGA device, sampling the signals to be observed to obtain sampling data, and writing the sampling data into external storage particles; reading out the sampling data stored in the external storage particles through a readback interface of an interconnection module in the FPGA device, and generating an actual waveform file from the read sampling data; And comparing the actual waveform file with the simulation waveform file of the signal to be observed, and generating the test information of the FPGA device based on a comparison result.

Description

FPGA device, testing system and method Technical Field The invention relates to the technical field of static storage, in particular to an FPGA device, a testing system and a testing method. Background Prototype verification of FPGA (Field Programmable GATE ARRAY ) refers to constructing a hardware model capable of truly simulating chip operation by using reconfigurable characteristics of FPGA before chip formal production, and performing software-hardware collaborative verification and system level test on the hardware model to discover and correct design defects in advance. To extend the memory capacity of the FPGA hardware model, a DDR controller can be instantiated within it and connected to large capacity DDR (DDR SDRAM, double rate synchronous dynamic random memory) granules. However, as integrated circuit complexity increases, signals to be observed in a design under test (DUT, design Under Test) tend to correspond to multiple asynchronous clock domains. If global asynchronous clock sampling is used, the sampling frequency of the global asynchronous clock must be twice the highest clock frequency in the multiple asynchronous clock domains according to the sampling theorem. At this time, the sampling frequency of the global asynchronous clock may be far higher than the signal frequency of the low-speed clock domain among the plurality of asynchronous clock domains, which may result in a large amount of redundant sampling data, not only wasting the DDR writing bandwidth, but also occupying the storage capacity, limiting the width and depth of the observable signal. Therefore, there is a need for improvement. Disclosure of Invention The invention provides an FPGA device, a testing system and a testing method, which are used for solving the technical problem that a large amount of redundant sampling data are generated by adopting a global asynchronous clock sampling mode in the traditional FPGA hardware model. The invention proposes an FPGA device comprising: The signal acquisition modules are used for receiving input signals with different clock frequencies, are configured with synchronous sampling clocks with the same clock frequency as the corresponding input signals, and synchronously sample the received input signals based on the synchronous sampling clocks to obtain corresponding sampling data; The processing module is used for distributing storage addresses to the sampled data obtained by sampling each signal acquisition module according to different storage address intervals of the external storage particles; the interconnection module is used for receiving the sampling data with different clock frequencies and the corresponding storage addresses transmitted by each signal acquisition module, and transmitting the sampling data and the corresponding storage addresses at the working clock frequency of the controller; and the controller is used for receiving the sampling data and the corresponding storage address transmitted by the interconnection module and writing the sampling data into the external storage particles according to the storage address corresponding to the sampling data. In one embodiment of the present invention, the signal acquisition module is further configured to access a working clock corresponding to an input signal in the module to be observed, and use the working clock as a synchronous sampling clock of the working clock, so as to synchronously sample the input signal. In one embodiment of the present invention, the processing module is further configured to sequentially allocate, in a storage address interval corresponding to the signal acquisition module, a corresponding storage address to the sampled data according to a generation sequence of the sampled data obtained by sampling by the signal acquisition module; the storage address intervals corresponding to the signal acquisition modules are a section of fixed and continuous address range in the external storage particles, and the storage address intervals corresponding to different signal acquisition modules are not overlapped with each other. In one embodiment of the present invention, the processing module is further configured to compare the storage address with the last storage address of the corresponding storage address interval after allocating the corresponding storage address to the sampled data, and when the storage address is the same as the last storage address of the corresponding storage address interval, continue allocating the storage address to the next sampled data from the first storage address of the storage address interval, so as to form continuous cyclic allocation of the storage address of the sampled data. In an embodiment of the present invention, the interconnection module is further configured to sequentially transmit, when the plurality of signal acquisition modules have sampling data to be transmitted at the same time, the sampling data and storage addresses thereof corresponding to the pl