CN-122019291-A - Method and device for testing multi-level memory and performance of DSP embedded system

CN122019291ACN 122019291 ACN122019291 ACN 122019291ACN-122019291-A

Abstract

The application provides a method and a device for testing multi-level memory and performance of a DSP embedded system, wherein the method comprises the steps of setting an address area of a protected area and an address area of a safety test area according to preset memory layout information in an initialization stage of the DSP embedded system; the method comprises the steps of analyzing a test instruction set sent by an upper computer to obtain an internal RAM test instruction and an external communication chip RAM test instruction, responding to the internal RAM test instruction, adopting dynamic memory mapping management to identify and avoid a protected area necessary for program operation, executing a memory test algorithm only in the safe test area to obtain a first test result, responding to the external communication chip RAM test instruction, backing up data of a block to be tested of an external communication chip to a temporary buffer area, testing the block to be tested to obtain a second test result, and returning the first test result and the second test result to the upper computer, so that the safety and coverage rate of system test can be improved.

Inventors

WANG YAJING
HU KEDI
LI MINGCUI
XIE ZHONGCHENG
ZHANG CHI

Assignees

北京航天新立科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260116

Claims (10)

1. A method for testing multi-level memory and performance of a DSP embedded system is characterized by comprising the following steps: setting an address area of a protected area and an address area of a safety test area according to preset memory layout information in an initialization stage of the DSP embedded system; Analyzing a test instruction set sent by an upper computer to obtain an internal RAM test instruction and an external communication chip RAM test instruction; Responding to the internal RAM test instruction, adopting dynamic memory mapping management, identifying and avoiding a protected area necessary for program operation, and executing a memory test algorithm only in the safety test area to obtain a first test result; Responding to the RAM test instruction of the external communication chip, backing up the data of the block to be tested of the external communication chip to the temporary buffer area, and then testing the block to be tested to obtain a second test result; And the first test result and the second test result are returned to the upper computer.
2. The method of claim 1, wherein the protected area comprises a code segment, a global data area, a heap, and a stack.
3. The method for testing multi-level memory and performance of a DSP embedded system according to claim 1, wherein said step of executing a memory testing algorithm only in said security test area comprises: and executing a March-C algorithm to perform complete test on the storage unit in the safety test area.
4. The method for testing multi-level memory and performance of a DSP embedded system according to claim 1, wherein after the step of analyzing the test instruction set sent by the host computer to obtain the internal RAM test instruction and the external communication chip RAM test instruction, further comprises: responding to the internal RAM test instruction, and performing integrity test on the address line of the memory by using a Walking 1/0 algorithm; the integrity test is performed on the data lines of the memory using Checkerboard algorithm.
5. The method for testing multi-level memory and performance of a DSP embedded system according to claim 1, wherein the step of testing the block to be tested of the external communication chip after backing up the data of the block to be tested to the temporary buffer area in response to the RAM test command of the external communication chip to obtain the second test result comprises: carrying out high-speed data transfer on the original data of the block to be tested of the external communication chip to a temporary buffer area through DMA, and then testing the block to be tested by adopting a March-C algorithm; and after the block to be tested is tested, carrying out high-speed data carrying on the original data to the block to be tested through DMA.
6. The utility model provides a testing arrangement of multilayer memory and performance of DSP embedded system which characterized in that includes: The address area setting module is used for setting the address area of the protected area and the address area of the safety test area according to preset memory layout information in the initialization stage of the DSP embedded system; The test instruction acquisition module is used for analyzing a test instruction set sent by the upper computer to obtain an internal RAM test instruction and an external communication chip RAM test instruction; The internal RAM test module is used for responding to the internal RAM test instruction, adopting dynamic memory mapping management, identifying and avoiding a protected area necessary for program operation, and executing a memory test algorithm only in the safety test area to obtain a first test result; The external communication chip testing module is used for responding to the external communication chip RAM testing instruction, backing up the data of the block to be tested of the external communication chip to the temporary buffer area, and then testing the block to be tested to obtain a second testing result; and the test result uploading module is used for transmitting the first test result and the second test result back to the upper computer.
7. The apparatus of claim 6, wherein the protected area comprises a code segment, a global data area, a heap, and a stack.
8. The device for testing multi-level memory and performance of a DSP embedded system according to claim 6, wherein said internal RAM testing module performs March-C algorithm complete testing of memory cells in said security test area.
9. The device for testing multi-level memory and performance of a DSP embedded system of claim 6, wherein said internal RAM testing module is further configured to perform an integrity test on address lines of the memory using a Walking 1/0 algorithm and to perform an integrity test on data lines of the memory using a Checkerboard algorithm.
10. The device for testing multi-level memory and performance of a DSP embedded system according to claim 6, wherein the external communication chip testing module is configured to perform high-speed data transfer of the original data of the block to be tested of the external communication chip to the temporary buffer area through DMA, then perform a test on the block to be tested by using March-C algorithm, and perform high-speed data transfer of the original data to the block to be tested through DMA after the test of the block to be tested is completed.

Description

Method and device for testing multi-level memory and performance of DSP embedded system Technical Field The application relates to the technical field of testing embedded systems, in particular to a method and a device for testing multi-level memory and performance of a DSP embedded system. Background DSP systems have a very wide range of applications in many high reliability areas, of which the importance is self-evident, so testing of the system is particularly critical. However, the testing techniques currently employed have two very prominent and serious problems. Firstly, there is a great disadvantage in terms of test safety. Conventional memory testing methods, such as the well-known March algorithm, are destructive in nature. Because the test is performed without fully considering the actual memory layout of the embedded system, such as programs, stacks and the like, which often reside in the memory, only the test work is performed blindly, the serious consequences of system crash are very likely to occur. This is better than in a precisely running machine, where the specific location and function of the various components are not known, and operation is done in the trade, which necessarily disturbs the normal order of operation of the whole system. Secondly, the test work can have adverse effects on the normal operation of the system. When testing the RAM of an external communication chip such as a network port, CAN controller, etc., this process will erase the configuration data and the cache data therein. Once these data are erased, communication is inevitably interrupted. In many online application scenarios, such communication interruption is completely unacceptable. Just like in a network environment in which data is transmitted in real time, if the data transmission is suddenly interrupted due to testing, huge trouble and loss are caused to the operation of the service of the whole system. Disclosure of Invention The application aims to overcome the defects and shortcomings in the prior art and provides a method and a device for testing multi-level memory and performance of a DSP embedded system. The first aspect of the embodiment of the application provides a method for testing multi-level memory and performance of a DSP embedded system, which comprises the following steps: setting an address area of a protected area and an address area of a safety test area according to preset memory layout information in an initialization stage of the DSP embedded system; Analyzing a test instruction set sent by an upper computer to obtain an internal RAM test instruction and an external communication chip RAM test instruction; Responding to the internal RAM test instruction, adopting dynamic memory mapping management, identifying and avoiding a protected area necessary for program operation, and executing a memory test algorithm only in the safety test area to obtain a first test result; Responding to the RAM test instruction of the external communication chip, backing up the data of the block to be tested of the external communication chip to the temporary buffer area, and then testing the block to be tested to obtain a second test result; And the first test result and the second test result are returned to the upper computer. As one embodiment, the protected region includes a code segment, a global data region, a heap, and a stack. As one embodiment, the step of executing the memory test algorithm only in the security test area includes: and executing a March-C algorithm to perform complete test on the storage unit in the safety test area. As an implementation manner, after the step of analyzing the test instruction set sent by the upper computer to obtain the internal RAM test instruction and the external communication chip RAM test instruction, the method further includes: responding to the internal RAM test instruction, and performing integrity test on the address line of the memory by using a Walking 1/0 algorithm; the integrity test is performed on the data lines of the memory using Checkerboard algorithm. As an implementation manner, in response to the RAM test instruction of the external communication chip, after backing up the data of the block to be tested of the external communication chip to the temporary buffer area, testing the block to be tested to obtain a second test result, including: carrying out high-speed data transfer on the original data of the block to be tested of the external communication chip to a temporary buffer area through DMA, and then testing the block to be tested by adopting a March-C algorithm; and after the block to be tested is tested, carrying out high-speed data carrying on the original data to the block to be tested through DMA. Compared with the prior art, the method for testing the multi-level memory and the performance of the DSP embedded system comprises the steps of setting an address area of a protected area and an address area of a safety test area accordin