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CN-122019329-A - Processor performance test method, device, equipment and storage medium

CN122019329ACN 122019329 ACN122019329 ACN 122019329ACN-122019329-A

Abstract

The invention discloses a method, a device, equipment and a storage medium for testing the performance of a processor, which relate to the technical field of performance testing and comprise the steps of compiling a performance testing program into a machine instruction, splitting the machine instruction into a plurality of instruction blocks, and marking each instruction block according to a target label; the target tag comprises an instruction type and a memory access mode, the instruction type comprises a floating point calculation type and an integer calculation type, performance data of each core when the processor executes tasks are obtained, the performance data comprise core utilization rate, cache hit rate, memory delay and inter-core communication delay, an instruction block is distributed to the target cores of the processor based on the target tag and the performance data so that the target cores execute the instruction block to obtain corresponding test data, the test data are recorded, and a performance test result of the processor is determined according to the test data. Thus, the invention can improve the effectiveness of performance test.

Inventors

  • Lin Ningya

Assignees

  • 山东博算智新信息科技有限公司

Dates

Publication Date
20260512
Application Date
20260130

Claims (10)

  1. 1. A method for testing performance of a processor, comprising: Compiling a performance test program into a machine instruction, splitting the machine instruction into a plurality of instruction blocks, and marking each instruction block according to a target tag, wherein the target tag comprises an instruction type and a memory access mode, and the instruction type comprises a floating point calculation type and an integer calculation type; Acquiring performance data of each kernel when a processor executes a task, wherein the performance data comprises a kernel utilization rate, a cache hit rate, a memory delay and inter-kernel communication delay; Distributing the instruction block to a target kernel of the processor based on the target tag and the performance data so that the target kernel executes the instruction block to obtain corresponding test data; and recording the test data, and determining the performance test result of the processor according to the test data.
  2. 2. The method for testing the performance of a processor according to claim 1, wherein, the splitting the machine instruction into instruction blocks includes: And splitting different functions in the machine instruction based on a preset low-correlation and fine-granularity principle to obtain a plurality of instruction blocks.
  3. 3. The method for testing the performance of a processor according to claim 1, wherein the acquiring performance data of each core when the processor executes the task comprises: And acquiring performance data of each kernel when the processor executes the task through a performance monitoring unit and a sensor inside the central processing unit.
  4. 4. The method of claim 1, wherein prior to said assigning the instruction block to the target core of the processor based on the target tag and the performance data, further comprising: Determining an allocation strategy of the instruction block, wherein the allocation strategy comprises a preset busy load pin strategy and a preset random pin strategy; the preset busy load pin strategy is a strategy for distributing the instruction block to a processor core with load meeting preset conditions, and the preset random pin strategy is a strategy for distributing the instruction block randomly; Correspondingly, the distributing the instruction block to the target kernel of the processor based on the target tag and the performance data so that the target kernel executes the instruction block to obtain corresponding test data includes: Determining a target kernel corresponding to the instruction block in the processor based on the target tag and the performance data according to the allocation policy; and distributing the instruction block to the target kernel so that the target kernel executes the instruction block to obtain corresponding test data, wherein the test data comprises the total execution time of the instruction block and a calculation result after the instruction block is executed.
  5. 5. The processor performance testing method of claim 1, further comprising: acquiring target data, wherein the target data comprises the temperature of a central processing unit, a main frequency, the utilization rate of a kernel and the occupation condition of a memory; And determining a target kernel of the processor based on the target tag and the performance data according to the target data so as to distribute the instruction block to the target kernel.
  6. 6. The method according to any one of claims 1 to 5, wherein determining the performance test result of the processor according to the test data comprises: after multiple tests, summarizing all the test data to obtain summarized data; and determining a performance test result of the processor according to the difference value between the current test data and the current average value of the summarized data.
  7. 7. The method of claim 6, wherein determining the performance test result of the processor based on the difference between the current test data and the current average of the summarized data comprises: if the difference between the current test data and the current average value of the summarized data is larger than or equal to a preset threshold value, generating a new average value according to the current test data and the summarized data, and re-jumping to the step of acquiring performance data of each kernel when the processor executes the task; and if the difference value between the current test data and the current average value of the summarized data is smaller than the preset threshold value, determining the current test data as a performance test result of the processor.
  8. 8. A processor performance testing apparatus, comprising: The system comprises a marking module, a target tag, a performance test module and a processing module, wherein the marking module is used for compiling a performance test program into a machine instruction, splitting the machine instruction into a plurality of instruction blocks and marking each instruction block according to the target tag; The performance data acquisition module is used for acquiring performance data of each kernel when the processor executes a task, wherein the performance data comprises a kernel utilization rate, a cache hit rate, memory delay and inter-kernel communication delay; The instruction block execution module is used for distributing the instruction block to a target kernel of the processor based on the target tag and the performance data so that the target kernel executes the instruction block to obtain corresponding test data; and the performance test result determining module is used for recording the test data and determining the performance test result of the processor according to the test data.
  9. 9. An electronic device, comprising: A memory for storing a computer program; A processor for executing the computer program to perform the steps of the processor performance testing method according to any one of claims 1 to 7.
  10. 10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the processor performance test method according to any of claims 1 to 7.

Description

Processor performance test method, device, equipment and storage medium Technical Field The present invention relates to the field of performance testing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for testing performance of a processor. Background With the increasing complexity of computer systems, conventional performance testing techniques often have difficulty covering a variety of different testing scenarios. The performance of a computer is closely related to its application scenarios, which may include CPU (Central Process Unit, central processing unit) intensive applications (e.g., scientific research), I/O (Input/Output) intensive applications (e.g., web servers), or memory intensive applications (e.g., video editing). The prior art scheme of the performance test of the processor is mainly realized by combining the multidimensional quantization index with the simulation scene. The basic method comprises the steps of measuring single/multi-line Cheng Yunsuan capacity such as integer floating point operation, memory bandwidth and delay test by using a standardized reference tool, verifying stability and heat dissipation design by continuous high load through pressure test, and analyzing and comparing power consumption efficiency with performance and energy consumption ratio. Best practice for evaluating the performance of a computer is to execute an actual application program on a machine, but for a multi-core processor, a conventional test program can only show performance under ideal conditions, and for a multi-process running in a daily use environment, the performance under a high load state can not show good performance. Therefore, how to solve the problems of the prior art that the test is not strict and the coverage of the result is incomplete facing the performance test scene of the multi-core processor is a problem to be considered by the person skilled in the art. Disclosure of Invention The embodiment of the invention aims to provide a method, a device, equipment and a storage medium for testing the performance of a processor, which can solve the problems of low test precision and incomplete coverage of results in the prior art, improve the effectiveness and accuracy of the performance test and provide references for optimizing the performance of the processor. The specific scheme is as follows: In a first aspect, the present invention provides a method for testing performance of a processor, including: Compiling a performance test program into a machine instruction, splitting the machine instruction into a plurality of instruction blocks, and marking each instruction block according to a target tag, wherein the target tag comprises an instruction type and a memory access mode; acquiring performance data of each kernel when the processor executes a task, wherein the performance data comprises a kernel utilization rate, a cache hit rate, a memory delay and inter-kernel communication delay; distributing the instruction block to a target kernel of the processor based on the target tag and the performance data so that the target kernel executes the instruction block to obtain corresponding test data; and recording the test data, and determining the performance test result of the processor according to the test data. Optionally, splitting the machine instruction into a number of instruction blocks includes: Different functions in the machine instruction are split based on a preset low-correlation and fine-granularity principle to obtain a plurality of instruction blocks. Optionally, obtaining performance data of each core when the processor executes the task includes: And acquiring performance data of each kernel when the processor executes the task through a performance monitoring unit and a sensor inside the central processing unit. Optionally, before distributing the instruction block to the target core of the processor based on the target tag and the performance data, further comprising: Determining an allocation strategy of the instruction block, wherein the allocation strategy comprises a preset busy load pin strategy and a preset random pin strategy; The method comprises the steps of setting a busy load pin strategy, a random pin strategy and a random pin strategy, wherein the busy load pin strategy is a strategy for distributing instruction blocks to processor cores with loads meeting preset conditions; Correspondingly, the instruction block is distributed to a target kernel of the processor based on the target tag and the performance data so that the target kernel executes the instruction block to obtain corresponding test data, and the method comprises the following steps: Determining a target kernel corresponding to the instruction block in the processor based on the target tag and the performance data according to the allocation policy; and distributing the instruction block to the target kernel so that the target kernel executes the in