CN-122019409-A - Data operation method and device

Abstract

The present disclosure relates to the field of computer technologies, and in particular, to a data operation method and apparatus. The method comprises the steps of searching a first table entry which is matched with an address of a first cache line in a submitted storage buffer area when an event of expelling the first cache line occurs in a cache, updating the data of the first cache line according to the data in the first table entry, expelling the first cache line to a lower-level cache and releasing the first table entry. By utilizing the embodiment of the specification, the data in the submitted storage buffer area is directly updated to the cache line which is evicted, and the cache line is transmitted to the lower-level cache, so that unnecessary operations are effectively reduced, the cache management efficiency is improved, and the system power consumption is reduced.

Inventors

• YANG RUIJIA

Assignees

• 成都群芯微电子科技有限公司

Dates

Publication Date

20260512

Application Date

20251224

Claims (16)

1. 1. A method of data manipulation, the method comprising: When an event of expelling a first cache line occurs in a cache, searching a first table item which is matched with the address of the first cache line in a submitting storage buffer zone CSB; updating the data of the first cache line according to the data in the first table item; and expelling the first cache line to a lower-level cache, and releasing the first table item.
2. 2. The method of claim 1, wherein upon occurrence of an event in the cache that evicts a first cache line, prior to looking up a first entry in the commit store buffer CSB having a match with an address of the first cache line, further comprising: When a storage operation is executed, the CSB searches a first cache line which is matched with a first address corresponding to the storage operation in the cache; and when the data is not written into the first cache line, an event of expelling the first cache line occurs in the cache.
3. 3. The method of claim 1, wherein evicting the first cache line to a lower level cache and freeing the first entry further comprises backing up the first entry to form a backup entry.
4. 4. A method according to claim 3, wherein the data of the backup entry matching the entry address of the CSB is updated when the cache line data in the cache is updated according to the data of the entry in the CSB.
5. 5. The method of claim 3, wherein evicting the first cache line into a lower level cache and releasing the first entry further comprises: when loading operation is executed, searching a target table item matched with a second address in the backup table item according to the second address corresponding to the loading operation; And loading the data of the target table entry.
6. 6. The method of claim 5, wherein, based on a second address corresponding to a load operation, searching for the following target entry or target cache line matching the second address: Searching a target table entry matched with the second address in the storage queue table entry; searching a target table item matched with the second address in the table items of the CSB; and searching a target cache line matched with the second address in the cache.
7. 7. The method of claim 6, further comprising, after obtaining a target entry or target cache line matching the second address of the load operation: and loading the data of the target table entry or the target cache line.
8. 8. The method of claim 7, wherein loading the data of the target entry or target cache line further comprises: and selecting a target table entry or a target cache line matched with the second address according to the priority to load.
9. 9. The method of claim 8, wherein the order of priority from big to small comprises: the queue entries, CSB entries, backup entries, and cache lines in the cache are stored.
10. 10. A data manipulation device, comprising: A lookup unit configured to, when an event of evicting a first cache line occurs in a cache, lookup a first entry in a commit store buffer CSB having an address matching the first cache line; An updating unit configured to update the data of the first cache line according to the data in the first table entry; An eviction unit configured to evict the first cache line into a lower level cache and release the first entry.
11. 11. A load/store unit comprising a store queue, a commit store buffer and a cache, said load/store unit performing the method of any one of claims 1 to 9.
12. 12. Load/store unit according to claim 11, further comprising backup means, said load/store unit performing the method according to any of the preceding claims 3-9.
13. 13. A processor comprising the load/store unit of claim 11 or 12.
14. 14. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor is the processor of claim 13.
15. 15. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the method of any of the preceding claims 1-9.
16. 16. A computer program product, characterized in that the computer program product comprises a computer program which, when executed by a processor, implements the method of any one of claims 1-9.

Description

Data operation method and device Technical Field The present disclosure relates to the field of computer technologies, and in particular, to a data operation method and apparatus. Background In computer systems, data storage devices (e.g., hard disks, databases, etc.) are relatively slow to read and write. Caching allows data to be accessed at a faster rate by storing frequently accessed data in a high-speed storage medium (e.g., memory, cache chip, etc.), reducing memory access latency. With the development of computer technology, a multi-level Cache architecture including a first-level data Cache (L1D Cache), a second-level data Cache (L2D Cache), and the like has emerged. The first-level data cache is usually integrated in the CPU chip, has smaller capacity but the highest speed, and the second-level data cache can be a larger-capacity cache integrated in the CPU chip or a cache chip positioned outside the CPU chip. Due to limited cache capacity, some cache lines of data can be evicted (evict) from the cache under certain conditions, and the cache lines of data are evicted to a lower-level cache or other storage media, so that the cache can accommodate new data. When some data is needed in the cache, the data of the needed cache line needs to be backfilled into the cache from the lower level cache or the storage medium. Both the eviction and the backfilling of the data in the cache are required to be performed in caches with different levels, and if the cache lines with the same address are frequently evicted and backfilled, the memory access times are increased, so that the system power consumption is increased. How to control data operation in the cache to reduce the frequent eviction and backfilling of cache lines with the same address, so as to reduce the system power consumption is a problem to be solved. Disclosure of Invention In order to solve the problems in the prior art, the embodiment of the specification provides a data operation method and device, which solve the problem that the system power consumption is high due to the fact that cache lines with the same address are frequently evicted and backfilled in the prior art. The embodiment of the specification provides a data operation method, which comprises the following steps: When an event of evicting a first cache line occurs in a cache, searching a first table entry which is matched with an address of the first cache line in a submitting storage buffer area (CSB); updating the data of the first cache line according to the data in the first table item; and expelling the first cache line to a lower-level cache, and releasing the first table item. As a further aspect of the present specification, when an event occurs in the cache to evict a first cache line, looking up a first entry in the Commit Store Buffer (CSB) having a match with an address of the first cache line further comprises: When a storage operation is executed, the CSB searches a first cache line which is matched with a first address corresponding to the storage operation in the cache; and when the data is not written into the first cache line, an event of expelling the first cache line occurs in the cache. As a further aspect of the present description, evicting the first cache line to a lower level cache and releasing the first entry further comprises backing up the first entry to form a backup entry. As yet a further aspect of the present description, when updating the cache line data in the cache based on the data of the CSB entry, the data of the backup entry matching the CSB entry address is updated. As another further aspect of the present disclosure, the evicting the first cache line into the lower level cache and releasing the first entry further includes: when loading operation is executed, searching a target table item matched with a second address in the backup table item according to the second address corresponding to the loading operation; And loading the data of the target table entry. As another further aspect of the present specification, according to a second address corresponding to a load operation, searching the following target table entry or target cache line matching the second address: Searching a target table entry matched with the second address in the storage queue table entry; searching a target table item matched with the second address in the table items of the CSB; and searching a target cache line matched with the second address in the cache. As another further aspect of the present specification, after obtaining the target entry or target cache line matching the second address of the load operation, further comprising: and loading the data of the target table entry or the target cache line. As another further aspect of the present specification, loading the data of the target entry or the target cache line further includes: and selecting a target table entry or a target cache line matched with the second address according to the priority to lo