CN-122019414-A - Cache consistency control method, consistency directory and processor chip

Abstract

The embodiment of the invention provides a cache consistency control method, a consistency directory and a processor chip, wherein the method comprises the steps of responding to an access request of a first core to a target cache line for the first time, distributing a first directory entry in the consistency directory; the first directory entry is used for recording an address tag of the target cache line and a first sharer, the first sharer comprises the first core, a second directory entry is distributed in the consistency directory in response to an access request of a second core to the target cache line, the second directory entry is used for recording a target way pointer and the second sharer, the target way pointer points to the first directory entry, the second sharer comprises the second core, and the number of the second cores is greater than or equal to 1. The embodiment of the invention can accurately represent the cache line copy position under the many-core condition while keeping the single directory entry width low, thereby saving the hardware cost and improving the system performance.

Inventors

• WANG MINGJIAN
• Tan Hongze

Assignees

• 龙芯中科技术股份有限公司

Dates

Publication Date

20260512

Application Date

20260409

Claims (16)

1. 1. The cache consistency control method is characterized by comprising the following steps: responding to an access request of a first core to a target cache line for the first time, and distributing a first directory entry in a consistency directory, wherein the first directory entry is used for recording an address label of the target cache line and a first sharer; And responding to an access request of a second core to the target cache line, distributing a second directory entry in the consistency directory, wherein the second directory entry is used for recording a target way pointer and a second sharer, the target way pointer points to the first directory entry, the second sharer comprises the second core, and the number of the second cores is greater than or equal to 1.
2. 2. The method of claim 1, wherein the second directory entry is in a first format in which the second sharer is recorded using a list of pointers, or in the case where the number of the second cores does not exceed a preset value And under the condition that the number of the second cores exceeds a preset value, the second directory entry is in a second format, the second directory entry in the second format further comprises a segment identifier and a sharer vector corresponding to the segment identifier, different segment identifiers are used for designating a plurality of different processor cores, and each bit of the sharer vector is used for indicating a second sharer.
3. 3. The method according to claim 1, wherein the method further comprises: Responding to a request of a first target core for removing the target cache line from a private cache, and searching a first target directory entry in the coherence directory based on a target address of the target cache line, wherein an address tag recorded in the first target directory entry is matched with an address tag corresponding to the target address, or a target way pointer recorded in the first target directory entry points to a first directory entry hit by the address tag; and clearing the record information of the first target core from each first target directory entry.
4. 4. The method according to claim 1, wherein the method further comprises: Responding to a request of a second target core for executing writing operation on the target cache line, and searching a second target directory entry in the consistency directory based on a target address of the target cache line, wherein an address tag recorded in the second target directory entry is matched with an address tag corresponding to the target address, or a target path pointer recorded in the second target directory entry points to a first directory entry hit by the address tag; And clearing all second directory entries in the second target directory entry, reserving only the first directory entry, and modifying a first sharer in the reserved first directory entry into the second target core.
5. 5. The method of claim 1, wherein the coherence directory has a plurality of sets of structures, each set including at least one path of directory entries, the directory entries of each path in each set corresponding to the same index, the method further comprising: When searching the consistency directory based on a target address, locating a hit target group according to an index corresponding to the target address; And determining hit directory entries matched with the address labels in the target group according to the address labels corresponding to the target addresses.
6. 6. The method of claim 1, wherein each directory entry in the coherence directory comprises a format identification indicating a type of the directory entry, wherein the type comprises a first directory entry, a second directory entry in the first format, a second directory entry in the second format, or an empty directory entry.
7. 7. The method of claim 1, further comprising a state identification in the first directory entry, the state identification being used to record a coherency state of the target cache line.
8. 8. The method of claim 1, wherein the coherence directory comprises an SRAM array of a group-associative architecture or a pattern-skew-associative architecture, wherein the SRAM array comprises a plurality of SRAM rows, each SRAM row corresponding to a group in the coherence directory, and wherein each SRAM row has a memory region divided into a plurality of ways, each memory region for independently storing a directory entry.
9. 9. A coherence directory for use in a multi-core processor system, the coherence directory comprising: A directory store configured to store a plurality of directory entries, and A catalog controller, coupled to the catalog store, configured to: responding to an access request of a first core to a target cache line for the first time, and distributing a first directory entry in a consistency directory, wherein the first directory entry is used for recording an address label of the target cache line and a first sharer; And responding to an access request of a second core to the target cache line, distributing a second directory entry in the consistency directory, wherein the second directory entry is used for recording a target way pointer and a second sharer, the target way pointer points to the first directory entry, the second sharer comprises the second core, and the number of the second cores is greater than or equal to 1.
10. 10. The coherence directory of claim 9, wherein in the event that the number of second cores does not exceed a preset value, the second directory entry is in a first format in which the second sharer is recorded using a list of pointers, or And under the condition that the number of the second cores exceeds a preset value, the second directory entry is in a second format, the second directory entry in the second format further comprises a segment identifier and a sharer vector corresponding to the segment identifier, different segment identifiers are used for designating a plurality of different processor cores, and each bit of the sharer vector is used for indicating a second sharer.
11. 11. The coherence directory of claim 9, wherein the directory controller is further configured to: The method comprises the steps of responding to a request of a first target core for removing a target cache line from a private cache, searching a first target directory entry in a consistency directory based on a target address of the target cache line, enabling an address tag recorded in the first target directory entry to be matched with an address tag corresponding to the target address or enabling a target path pointer recorded in the first target directory entry to point to a first directory entry hit by the address tag, enabling the first target core to be recorded in the first target directory entry, and clearing recording information of the first target core from each first target directory entry.
12. 12. The coherence directory of claim 9, wherein the directory controller is further configured to: Responding to a request of a second target core for executing writing operation on the target cache line, searching a second target directory entry in the consistency directory based on a target address of the target cache line, wherein an address tag recorded in the second target directory entry is matched with an address tag corresponding to the target address, or a target way pointer recorded in the second target directory entry points to a first directory entry hit by the address tag, the second target core is recorded in the second target directory entry, all the second directory entries in the second target directory entry are cleared, only the first directory entry is reserved, and a first sharer in the reserved first directory entry is modified to be the second target core.
13. 13. A processor chip, comprising: A plurality of processor cores, each core comprising a private cache for storing copies of cache lines; a network on chip providing an interconnection communication path between the plurality of processor cores and the coherence directory subsystem, and A coherence directory subsystem coupled with the network on chip configured to: responding to an access request of a first core to a target cache line for the first time, and distributing a first directory entry in a consistency directory, wherein the first directory entry is used for recording an address label of the target cache line and a first sharer; And responding to an access request of a second core to the target cache line, distributing a second directory entry in the consistency directory, wherein the second directory entry is used for recording a target way pointer and a second sharer, the target way pointer points to the first directory entry, the second sharer comprises the second core, and the number of the second cores is greater than or equal to 1.
14. 14. The processor chip of claim 13, wherein the second directory entry is in a first format in which the second sharer is recorded using a list of pointers in the case where the number of the second cores does not exceed a preset value, or And under the condition that the number of the second cores exceeds a preset value, the second directory entry is in a second format, the second directory entry in the second format further comprises a segment identifier and a sharer vector corresponding to the segment identifier, different segment identifiers are used for designating a plurality of different processor cores, and each bit of the sharer vector is used for indicating a second sharer.
15. 15. The processor chip of claim 13, wherein the coherence directory subsystem is further configured to: The method comprises the steps of responding to a request of a first target core for removing a target cache line from a private cache, searching a first target directory entry in a consistency directory based on a target address of the target cache line, enabling an address tag recorded in the first target directory entry to be matched with an address tag corresponding to the target address or enabling a target path pointer recorded in the first target directory entry to point to a first directory entry hit by the address tag, enabling the first target core to be recorded in the first target directory entry, and clearing recording information of the first target core from each first target directory entry.
16. 16. The processor chip of claim 13, wherein the coherence directory subsystem is further configured to: Responding to a request of a second target core for executing writing operation on the target cache line, searching a second target directory entry in the consistency directory based on a target address of the target cache line, wherein an address tag recorded in the second target directory entry is matched with an address tag corresponding to the target address, or a target way pointer recorded in the second target directory entry points to a first directory entry hit by the address tag, the second target core is recorded in the second target directory entry, all the second directory entries in the second target directory entry are cleared, only the first directory entry is reserved, and a first sharer in the reserved first directory entry is modified to be the second target core.

Description

Cache consistency control method, consistency directory and processor chip Technical Field The present invention relates to the field of computer technologies, and in particular, to a cache coherency control method, a coherency directory, and a processor chip. Background In a multi-core processor system, each core typically has a private cache to increase the speed of data access. However, when multiple cores access and modify the same data in shared memory at the same time, data inconsistency problems may occur between private caches, and therefore a cache coherency protocol is required to ensure proper execution. In cache coherency protocols, a coherence Directory (Directory) is widely used to track the distribution of shared data in each core cache. A cache line may be shared by multiple cores where there is a copy of the cache line in the private caches of the cores. To represent all possible copy location scenarios (i.e., all possible shared scenarios of the cache line), a bit vector of length equal to the number of processor cores is required, which makes it difficult to extend the directory entry width to the case of a many-core processor as the number of cores increases. As processors enter the many-core age, the number of cores increases to hundreds or even thousands, and conventional directory structures face the dilemma that if accurate records are maintained, the directory entry bit width grows linearly with the number of cores, and the hardware overhead is excessive, affecting the system performance. Disclosure of Invention In view of the above problems, embodiments of the present invention are provided to provide a cache coherency control method that overcomes the above problems or at least partially solves the above problems, and can accurately represent the cache line copy location in many-core situations while maintaining a low single directory entry width, so that hardware overhead can be saved, and system performance can be improved. Correspondingly, the embodiment of the invention also provides a consistency catalog and a processor chip, which are used for ensuring the realization and the application of the method. In a first aspect, an embodiment of the present invention discloses a cache consistency control method, where the method includes: responding to an access request of a first core to a target cache line for the first time, and distributing a first directory entry in a consistency directory, wherein the first directory entry is used for recording an address label of the target cache line and a first sharer; And responding to an access request of a second core to the target cache line, distributing a second directory entry in the consistency directory, wherein the second directory entry is used for recording a target way pointer and a second sharer, the target way pointer points to the first directory entry, the second sharer comprises the second core, and the number of the second cores is greater than or equal to 1. In a second aspect, an embodiment of the present invention discloses a coherence directory applied to a multi-core processor system, where the coherence directory includes: A directory store configured to store a plurality of directory entries, and A catalog controller, coupled to the catalog store, configured to: responding to an access request of a first core to a target cache line for the first time, and distributing a first directory entry in a consistency directory, wherein the first directory entry is used for recording an address label of the target cache line and a first sharer; And responding to an access request of a second core to the target cache line, distributing a second directory entry in the consistency directory, wherein the second directory entry is used for recording a target way pointer and a second sharer, the target way pointer points to the first directory entry, the second sharer comprises the second core, and the number of the second cores is greater than or equal to 1. In a third aspect, an embodiment of the present invention discloses a processor chip, including: A plurality of processor cores, each core comprising a private cache for storing copies of cache lines; a network on chip providing an interconnection communication path between the plurality of processor cores and the coherence directory subsystem, and A coherence directory subsystem coupled with the network on chip configured to: responding to an access request of a first core to a target cache line for the first time, and distributing a first directory entry in a consistency directory, wherein the first directory entry is used for recording an address label of the target cache line and a first sharer; And responding to an access request of a second core to the target cache line, distributing a second directory entry in the consistency directory, wherein the second directory entry is used for recording a target way pointer and a second sharer, the target way pointer points to th