CN-122019420-A - Memory access method, address transmission method and related products

Abstract

The application provides a memory access method, an address transmission method, a device, a chip network, an electronic device and electronic equipment, and relates to the technical field of chips. When the memory access among the chip nodes is realized in the chip network, the memory access among the chip nodes in the chip network can be realized by adopting the unique target identifier of the second chip node and the target local physical address in the memory space to be accessed to access the second chip node, so that the route of the accessed chip node can be realized by adding the unique target identifier while the physical address transmission is maintained. Compared with the scheme using the global physical address, the security of the address transmission is changed, and the method is more suitable for the dynamic change condition of the chip network, and can reduce the cost of a routing table in the chip network.

Inventors

• TIAN HONG
• LAN KEJIA
• SUN JIE

Assignees

• 海光信息技术股份有限公司

Dates

Publication Date

20260512

Application Date

20260126

Claims (19)

1. 1. The memory access method is characterized by being applied to a first chip node of a chip network, wherein the chip network comprises a plurality of chip nodes, the chip nodes are in communication connection through a first switch node, the first chip node is any chip node in the chip network, and the method comprises the following steps: In response to obtaining a target virtual address of a memory space to be accessed, obtaining a target physical address corresponding to the target virtual address from a local page table; the second chip node is any chip node except the first chip node in the chip network; Sending a memory access request to a second chip node with a target unique identifier in the target physical address through the first switch node under the condition that the target physical address belongs to the second chip node, wherein the memory access request comprises a target local physical address in the target physical address; And receiving feedback of the second chip node through the first switch node.
2. 2. The memory access method of claim 1, wherein in response to obtaining a target virtual address of a memory space to be accessed, obtaining a target physical address corresponding to the target virtual address from a local page table comprises: in response to obtaining a target virtual address of a memory space to be accessed, searching a target page table entry corresponding to the target virtual address from the local page table; Determining a value at a first specified location of the target page table entry; Obtaining the target unique identifier from a second specified location of the target page table entry and the target local physical address from a third specified location of the target page table entry, if the value at the first specified location is the first value; and splicing the target unique identifier and the target local physical address to obtain the target physical address.
3. 3. The memory access method of claim 1, wherein the method further comprises: And accessing the memory space to be accessed in the memory of the first chip node according to the target physical address under the condition that the target physical address belongs to the first chip node.
4. 4. The memory access method of claim 3, wherein in response to obtaining a target virtual address of a memory space to be accessed, obtaining a target physical address corresponding to the target virtual address from a local page table comprises: in response to obtaining a target virtual address of a memory space to be accessed, searching a target page table entry corresponding to the target virtual address from the local page table; Determining a value at a first specified location of the target page table entry; The target physical address is obtained from a third specified location of the target page table entry, where the value at the first specified location is a second value.
5. 5. The memory access method of any of claims 1-4, wherein the chip node is a deep computer chip DCU and the target unique identifier is a DCU identifier of the second chip node.
6. 6. The memory access method is characterized by being applied to a first switch node of a chip network, wherein the chip network comprises a plurality of chip nodes, the chip nodes are in communication connection through the first switch node, and the method comprises the following steps: Responding to a first memory access request transmitted by a first chip node, and acquiring a target unique identifier from the memory access request; forwarding a second memory access request to a second chip node with the target unique identifier, wherein the second memory access request comprises a target local physical address; And receiving feedback information of the second chip node and forwarding the feedback information to the first chip node.
7. 7. The memory access method of claim 6, wherein the second memory access request is the first memory access request.
8. 8. The memory access method is characterized by being applied to a second chip node of a chip network, wherein the chip network comprises a plurality of chip nodes, the chip nodes are in communication connection through a first switch node, the second chip node is any chip node in the chip network, and the method comprises the following steps: The method comprises the steps of receiving a memory access request transmitted by a first switch node, wherein the first switch node determines a second chip node according to a target unique identifier transmitted by the first chip node, and the first chip node is any chip node except the second chip node in a chip network; feeding back data at the target local physical address to the first switch node when the memory access request is a data read request; and under the condition that the memory access request is a data write request, writing data corresponding to the data write request into the target local physical address, and feeding back write response information to the first switch node.
9. 9. The address transmission method is characterized by being applied to a first chip node of a chip network, wherein the chip network comprises a plurality of chip nodes, the chip nodes are in communication connection through a second switch node and an interface node, the first chip node is any chip node in the chip network, and the method comprises the following steps: receiving a to-be-built physical address of a second chip node transmitted by the second switch node, wherein the to-be-built physical address comprises a unique identifier of the second chip node and a local physical address of the second chip node; And establishing a page table entry in a local page table according to the unique identifier of the second chip node and the local physical address of the second chip node, wherein the unique identifier of the second chip node and the local physical address of the second chip node are recorded in the page table entry, and the page table entry uniquely corresponds to a virtual address.
10. 10. The method of address transmission according to claim 9, wherein prior to receiving the second chip node to-be-tabulated physical address from the second switch node, the method further comprises: And sending an access application to the second chip node.
11. 11. The address transmission method of claim 9, wherein the value at the first specified location of the page table entry is a first value.
12. 12. The address transmission method is characterized by being applied to interface nodes of a chip network, wherein the chip network comprises a plurality of chip nodes, the chip nodes are in communication connection with the interface nodes through a second switch node, and the method comprises the following steps: Receiving a unique identifier of a second chip node and a local physical address of the second chip node, wherein the unique identifier is transmitted by the second switch node; splicing the unique identifier and the local physical address to obtain a physical address of the second chip node to be built; And sending the to-be-built table physical address to an interface node of the opposite terminal, so that the interface node of the opposite terminal sends the to-be-built table physical address to a first chip node through a second switch node of the opposite terminal, wherein the first chip node is any chip node except the second chip node in the chip network.
13. 13. The address transmission method is characterized by being applied to a second chip node of a chip network, wherein the chip network comprises a plurality of chip nodes, the chip nodes are in communication connection through a second switch node and an interface node, the second chip node is any chip node in the chip network, and the method comprises the following steps: acquiring a unique identifier of the self and a local physical address of a local memory; And transmitting the unique identification of the second switch node and the local physical address to the first chip node through communication of the second switch node and an interface node.
14. 14. The address transmission method of claim 13, wherein before obtaining the unique identification of the device and the local physical address of the local memory, the method further comprises: and responding to the received access application of the first chip node, and applying for a memory space in a local memory, wherein the first chip node is any chip node except the second chip node in the chip network, and the local physical address is the local physical address of the applied memory space.
15. 15. The address transmission method of claim 13 or 14, wherein the chip node is a deep computer chip DCU, and the unique identification is a DCU identifier of the second chip node.
16. 16. A chip comprising a memory management unit and a memory, wherein the memory management unit is configured to perform the method according to any one of claims 1-5, 8-11, 13-15.
17. 17. A chip network, comprising a plurality of chip nodes, wherein the chip nodes are in communication connection through a first switch node, and are also in communication connection through a second switch node and an interface node, and each chip node is realized by the chip as claimed in claim 16.
18. 18. An electronic device comprising the network of chips of claim 17.
19. 19. An electronic device comprising the electronic device of claim 18.

Description

Memory access method, address transmission method and related products Technical Field The present application relates to the field of chip technologies, and in particular, to a memory access method, an address transmission device, a chip network, an electronic device, and an electronic apparatus. Background In a large-scale chip network, a large number of chip nodes in the chip network exchange data point-to-point with each other. During the data exchange, the address is used as a unique identifier throughout the network system. Currently, the addresses in the chip network are required to be uniformly arranged according to the transmitted nodes, and the global physical address is transmitted. However, the security of address transmission cannot be ensured by directly using the global physical address for data transmission. Meanwhile, because the global physical addresses are uniformly distributed, if the chip nodes are newly added or modified in the chip network, uniform modification of the global physical addresses is needed, and the workload is high, so that the dynamic change of the chip network is not facilitated. In addition, the routing is performed by using the global physical address in the chip network, and the routing table needs to record the complete global physical address, so that a large routing table overhead is generated. Disclosure of Invention The embodiment of the application aims to provide a memory access method, an address transmission device, a chip network, an electronic device and electronic equipment, which are used for improving the safety of address transmission, being more suitable for dynamic change of the chip network and reducing the cost of a routing table in the chip network. The embodiment of the application provides a memory access method which is applied to a first chip node of a chip network, wherein the chip network comprises a plurality of chip nodes which are connected through a first switch node in a communication mode, the first chip node is any chip node in the chip network, the method comprises the steps of responding to a target virtual address obtained to a memory space to be accessed, obtaining a target physical address corresponding to the target virtual address from a local page table, wherein the target physical address comprises a target unique identifier of the second chip node and a target local physical address in the memory space to be accessed in a case that the target physical address belongs to a second chip node, the second chip node is any chip node except the first chip node in the chip network, sending an access request to the second chip node with the target unique identifier through the first switch node in a case that the target physical address belongs to the second chip node, and receiving the memory access request by the first switch node through the first switch node. In the implementation scheme, when the memory access among the chip nodes is realized in the chip network, the memory access among the chip nodes in the chip network can be realized by adopting the target unique identifier of the second chip node and the target local physical address in the memory space to be accessed in the second chip node for access, so that the route of the accessed chip node can be realized by adding the target unique identifier while the physical address transmission is maintained. Compared with the related art, the global physical address is not transmitted any more, even if the target physical address leaks in the transmission process, if the unique identification of each chip node and the physical address allocation scheme of the inside of each chip node are not clear, the data positioning cannot be directly realized based on the target physical address, so that the safety is improved to a certain extent. In addition, based on the scheme of the application, when the chip network is changed, only the identification of the chip node in the change routing table is required to be corresponding, and the modification of the physical address is not required, so that the method can be more suitable for the dynamic change of the chip network. In addition, the routing table in the first switch node only needs to record the unique identifier of each chip node, and does not need to record the global physical address, and the size of the unique identifier of each chip node is far smaller than that of the global physical address, so that the cost of the routing table in the chip network can be reduced. Optionally, the method comprises the steps of responding to the acquisition of a target virtual address of a memory space to be accessed, acquiring a target physical address corresponding to the target virtual address from a local page table, searching a target page table entry corresponding to the target virtual address from the local page table, determining a value at a first appointed position of the target page table entry, acquiring the target unique identif